@@ -4159,18 +4159,18 @@ bool AMDGPULegalizerInfo::legalizeCTLZ_CTTZ(MachineInstr &MI,
4159
4159
bool AMDGPULegalizerInfo::legalizeCTLZ_ZERO_UNDEF (MachineInstr &MI,
4160
4160
MachineRegisterInfo &MRI,
4161
4161
MachineIRBuilder &B) const {
4162
- auto Dst = MI.getOperand (0 ).getReg ();
4163
- auto Src = MI.getOperand (1 ).getReg ();
4164
- auto DstTy = MRI.getType (Dst);
4165
- auto SrcTy = MRI.getType (Src);
4166
- auto NumBits = SrcTy.getSizeInBits ();
4162
+ Register Dst = MI.getOperand (0 ).getReg ();
4163
+ Register Src = MI.getOperand (1 ).getReg ();
4164
+ LLT DstTy = MRI.getType (Dst);
4165
+ LLT SrcTy = MRI.getType (Src);
4166
+ TypeSize NumBits = SrcTy.getSizeInBits ();
4167
4167
4168
4168
assert (NumBits < 32u );
4169
4169
4170
4170
auto ShiftAmt = B.buildConstant (S32, 32u - NumBits);
4171
- Src = B.buildAnyExt (S32, {Src}).getReg (0u );
4172
- Src = B.buildLShr (S32, {Src }, ShiftAmt).getReg (0u );
4173
- B.buildInstr (AMDGPU::G_AMDGPU_FFBH_U32, {Dst}, {Src });
4171
+ auto Tmp = B.buildAnyExt (S32, {Src}).getReg (0u );
4172
+ Tmp = B.buildLShr (S32, {Tmp }, ShiftAmt).getReg (0u );
4173
+ B.buildInstr (AMDGPU::G_AMDGPU_FFBH_U32, {Dst}, {Tmp });
4174
4174
MI.eraseFromParent ();
4175
4175
return true ;
4176
4176
}
0 commit comments