[ConstraintElim] icmp spred x, y implies icmp samesign upred x, y

[dtcxzyw]

Alive2: https://alive2.llvm.org/ce/z/ZNNbj_

define i1 @src(i32 %x, i32 %y) {
entry:
  %cond = icmp sgt i32 %x, %y
  br i1 %cond, label %if.then, label %if.else

if.then:
  %cmp = icmp samesign ugt i32 %x, %y
  ret i1 %cmp

if.else:
  ret i1 false
}

define i1 @tgt(i32 %x, i32 %y) {
entry:
  %cond = icmp sgt i32 %x, %y
  br i1 %cond, label %if.then, label %if.else

if.then:
  ret i1 true

if.else:
  ret i1 false
}

We already perform similar optimizations in #115893.

[dtcxzyw]

Another case:

define i1 @_ZN17double_conversionL15FillFractionalsEmiiNS_6VectorIcEEPiS2_(i32 %exponent) {
entry:
  %cmp = icmp samesign ult i32 %exponent, 65
  br i1 %cmp, label %for.cond.preheader, label %if.else

for.cond.preheader:                               ; preds = %entry
  ret i1 false

if.else:                                          ; preds = %entry
  %cmp12.i = icmp samesign ugt i32 %exponent, -65
  ret i1 %cmp12.i
}

[fhahn]

cc @zjaffal @artagnon