[VectorCombine] Recognise reduction patterns from extract+binop+shuffle chains

[RKSimon]

define i16 @test_reduce_v8i16(<8 x i16> %a0) local_unnamed_addr #0 {
  %1 = shufflevector <8 x i16> %a0, <8 x i16> poison, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 poison, i32 poison, i32 poison, i32 poison>
  %2 = tail call <8 x i16> @llvm.umin.v8i16(<8 x i16> %a0, <8 x i16> %1)
  %3 = shufflevector <8 x i16> %2, <8 x i16> poison, <8 x i32> <i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
  %4 = tail call <8 x i16> @llvm.umin.v8i16(<8 x i16> %2, <8 x i16> %3)
  %5 = shufflevector <8 x i16> %4, <8 x i16> poison, <8 x i32> <i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
  %6 = tail call <8 x i16> @llvm.umin.v8i16(<8 x i16> %4, <8 x i16> %5)
  %7 = extractelement <8 x i16> %6, i64 0
  ret i16 %7
}

Recognise that patterns such as this can fold to a llvm.vector.reduce.umin.v8i16(%a0) intrinsic call (costs permitting)

Noticed when reviewing #144231

[Rajveer100]

@RKSimon
I believe we would want to create a fold method for reducing the pattern in visitCallInst and replace uses with the llvm.vector.reduce.umin.v8i16? If this works well, we could possibly then extend this to other types too?

Let me know if this is the right direction to proceed.

[RKSimon]

This should be in VectorCombine for actual cost analysis - probably creating something similar to SelectionDAG::matchBinOpReduction to match the chain