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backend:X86backend:X86 Scheduler ModelsAccuracy of X86 scheduler modelsAccuracy of X86 scheduler modelsbugzillaIssues migrated from bugzillaIssues migrated from bugzilla
Description
Bugzilla Link | 36887 |
Resolution | FIXED |
Resolved on | Apr 24, 2018 10:11 |
Version | trunk |
OS | All |
Blocks | #31672 |
CC | @RKSimon |
Fixed by commit(s) | 330714,330737 |
Extended Description
For example
PEXTRBmr has WriteShuffleLd WriteRMW
But the instruction doesn't load anything.
Affected instructions
EXTRACTPSmr
PEXTRBmr
PEXTRDmr
PEXTRQmr
PEXTRWmr
VCVTPS2PHYmr
VCVTPS2PHmr
VEXTRACTPSmr
VPEXTRBZmr
VPEXTRBmr
VPEXTRDZmr
VPEXTRDmr
VPEXTRQZmr
VPEXTRQmr
VPEXTRWZmr
VPEXTRWmr
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backend:X86backend:X86 Scheduler ModelsAccuracy of X86 scheduler modelsAccuracy of X86 scheduler modelsbugzillaIssues migrated from bugzillaIssues migrated from bugzilla