Skip to content

[MIPS] Missing ANDI optimization #42826

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Closed
arichardson opened this issue Sep 27, 2019 · 1 comment · Fixed by #97689
Closed

[MIPS] Missing ANDI optimization #42826

arichardson opened this issue Sep 27, 2019 · 1 comment · Fixed by #97689
Assignees
Labels
backend:MIPS bugzilla Issues migrated from bugzilla

Comments

@arichardson
Copy link
Member

Bugzilla Link 43481
Version trunk
OS All

Extended Description

We noticed that clang generates unnecessary SLL instructions in one of our benchmark hot paths (and apparently GCC does not): https://godbolt.org/z/xKcCqT

Consider

#include <stdint.h>

uint64_t foo(uint64_t a)
{
    uint64_t b = a / 16;
    uint64_t c = b & 0x7UL;
    return ((uint64_t)1UL << c);
}

At present, the MIPS backend produces:

foo(unsigned long):                                # @&#8203;foo(unsigned long)
        sll     $1, $4, 0
        srl     $1, $1, 4
        andi    $1, $1, 7
        daddiu  $2, $zero, 1
        jr      $ra
        dsllv   $2, $2, $1

The sll is introduced because the srl requires that its input be zero extended (which, well, seems silly, but so it goes). In any case, because andi has a 16-bit immediate, some arithmetic and lookahead could find that 0x7 << 4 fits and so make this be

        andi    $1, $4, 0x70
        srl     $1, $1, 4
        daddiu  $2, $zero, 1
        jr      $ra
        dsllv   $2, $2, $1

Alternatively, whatever's concluding that it can use 32-bit values internally could stop doing that and this could instead just be

        dsrl    $1, $4, 4
        andi    $1, $1, 7
        daddiu  $2, $zero, 1
        jr      $ra
        dsllv   $2, $2, $1

This problem was found by Nathaniel Wesley Filardo and reported as CTSRD-CHERI/llvm-project#343

@arichardson
Copy link
Member Author

assigned to @atanasyan

@llvmbot llvmbot transferred this issue from llvm/llvm-bugzilla-archive Dec 10, 2021
@wzssyqa wzssyqa self-assigned this Apr 22, 2024
yingopq added a commit to yingopq/llvm-project that referenced this issue Jul 4, 2024
1. Add MipsPat to optimize (andi (srl (truncate i64 $1), x), y) to
   (andi (truncate (dsrl i64 $1, x)), y).
2. Add MipsPat to optimize (ext (truncate i64 $1), x, y) to
   (truncate (dext i64 $1, x, y)).

The assembly result is the same as gcc.

Fix llvm#42826
yingopq added a commit to yingopq/llvm-project that referenced this issue Aug 5, 2024
1. Add MipsPat to optimize (andi (srl (truncate i64 $1), x), y) to
   (andi (truncate (dsrl i64 $1, x)), y).
2. Add MipsPat to optimize (ext (truncate i64 $1), x, y) to
   (truncate (dext i64 $1, x, y)).

The assembly result is the same as gcc.

Fix llvm#42826
yingopq added a commit to yingopq/llvm-project that referenced this issue Aug 7, 2024
yingopq added a commit to yingopq/llvm-project that referenced this issue Aug 7, 2024
1. Add MipsPat to optimize (andi (srl (truncate i64 $1), x), y) to
   (andi (truncate (dsrl i64 $1, x)), y).
2. Add MipsPat to optimize (ext (truncate i64 $1), x, y) to
   (truncate (dext i64 $1, x, y)).

The assembly result is the same as gcc.

Fix llvm#42826
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
backend:MIPS bugzilla Issues migrated from bugzilla
Projects
None yet
Development

Successfully merging a pull request may close this issue.

2 participants