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[MIPS] Missing ANDI optimization #42826
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yingopq
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1. Add MipsPat to optimize (andi (srl (truncate i64 $1), x), y) to (andi (truncate (dsrl i64 $1, x)), y). 2. Add MipsPat to optimize (ext (truncate i64 $1), x, y) to (truncate (dext i64 $1, x, y)). The assembly result is the same as gcc. Fix llvm#42826
yingopq
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1. Add MipsPat to optimize (andi (srl (truncate i64 $1), x), y) to (andi (truncate (dsrl i64 $1, x)), y). 2. Add MipsPat to optimize (ext (truncate i64 $1), x, y) to (truncate (dext i64 $1, x, y)). The assembly result is the same as gcc. Fix llvm#42826
yingopq
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yingopq
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Aug 7, 2024
1. Add MipsPat to optimize (andi (srl (truncate i64 $1), x), y) to (andi (truncate (dsrl i64 $1, x)), y). 2. Add MipsPat to optimize (ext (truncate i64 $1), x, y) to (truncate (dext i64 $1, x, y)). The assembly result is the same as gcc. Fix llvm#42826
arichardson
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Extended Description
We noticed that clang generates unnecessary SLL instructions in one of our benchmark hot paths (and apparently GCC does not): https://godbolt.org/z/xKcCqT
Consider
At present, the MIPS backend produces:
The
sll
is introduced because thesrl
requires that its input be zero extended (which, well, seems silly, but so it goes). In any case, becauseandi
has a 16-bit immediate, some arithmetic and lookahead could find that0x7 << 4
fits and so make this beAlternatively, whatever's concluding that it can use 32-bit values internally could stop doing that and this could instead just be
This problem was found by Nathaniel Wesley Filardo and reported as CTSRD-CHERI/llvm-project#343
The text was updated successfully, but these errors were encountered: