[AMDGPU] Backend assertion hit during codegen

[jhuber6]

The AMDGPU backend hits an assertion while attempting to get a register for the following reduced code https://godbolt.org/z/46dccMErP. This only occurs with assertions enabled and seems to work fine with a standard build.

target triple = "amdgcn-amd-amdhsa"

define void @foo() #0 {
  %1 = alloca [2 x i8], align 1, addrspace(5)
  %2 = getelementptr [2 x i8], ptr addrspace(5) %1, i32 0, i32 1
  br label %._crit_edge

._crit_edge:                                      ; preds = %.._crit_edge_crit_edge, %0
  store i8 1, ptr addrspace(5) %2, align 1
  br label %3

3:                                                ; preds = %3, %._crit_edge
  %4 = phi i64 [ 1, %3 ], [ 0, %._crit_edge ]
  %5 = trunc i64 %4 to i32
  %6 = getelementptr i8, ptr addrspace(5) %1, i32 %5
  %7 = load i8, ptr addrspace(5) %6, align 1
  %8 = getelementptr i8, ptr null, i64 %4
  store i8 %7, ptr %8, align 1
  br i1 false, label %.._crit_edge_crit_edge, label %3

.._crit_edge_crit_edge:                           ; preds = %3
  br label %._crit_edge
}

attributes #0 = { "target-cpu"="gfx1030" }

**llc: /root/llvm-project/llvm/include/llvm/CodeGen/MachineOperand.h:370: llvm::Register llvm::MachineOperand::getReg() const: Assertion `isReg() && "This is not a register operand!"' failed.**

[llvmbot]

@llvm/issue-subscribers-backend-amdgpu

The AMDGPU backend hits an assertion while attempting to get a register for the following reduced code https://godbolt.org/z/46dccMErP. This only occurs with assertions enabled and seems to work fine with a standard build. ```llvm target triple = "amdgcn-amd-amdhsa"

define void @foo() #0 {
%1 = alloca [2 x i8], align 1, addrspace(5)
%2 = getelementptr [2 x i8], ptr addrspace(5) %1, i32 0, i32 1
br label %._crit_edge

._crit_edge: ; preds = %.._crit_edge_crit_edge, %0
store i8 1, ptr addrspace(5) %2, align 1
br label %3

3: ; preds = %3, %._crit_edge
%4 = phi i64 [ 1, %3 ], [ 0, %._crit_edge ]
%5 = trunc i64 %4 to i32
%6 = getelementptr i8, ptr addrspace(5) %1, i32 %5
%7 = load i8, ptr addrspace(5) %6, align 1
%8 = getelementptr i8, ptr null, i64 %4
store i8 %7, ptr %8, align 1
br i1 false, label %.._crit_edge_crit_edge, label %3

.._crit_edge_crit_edge: ; preds = %3
br label %._crit_edge
}

attributes #0 = { "target-cpu"="gfx1030" }

llc: /root/llvm-project/llvm/include/llvm/CodeGen/MachineOperand.h:370: llvm::Register llvm::MachineOperand::getReg() const: Assertion `isReg() && "This is not a register operand!"' failed.

</details>

[jayfoad]

Looks like SIPeepholeSDWA was not expecting to see an instruction like %9:vgpr_32 = V_LSHLREV_B16_e64 8, 1, implicit $exec. Normally this would be folded away, since both operands are constant. It should be simple to fix SIPeepholeSDWA to be more robust.