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[AArch64] Missed vectorisation opportunity (tsvc, s172) #71517
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@llvm/issue-subscribers-backend-aarch64 Author: Sjoerd Meijer (sjoerdmeijer)
We are not vectorising kernel s172 from TSVS and are 3x behind compared to GCC as a result. Compile this input with `-O3 -ffast-math -mcpu=neoverse-v2`:
Clang's codegen:
GCC's codegen:
See also: TODO: root cause analysis. |
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… versioning This commit enable the vectorization for the case from llvm#71517. float s172(int xa, int xb) { for (int i = xa - 1; i < 32000; i += xb) a[i] += b[i]; } By assuming the stride as one and generating the runtime checking to guard the vectorized loop, it seems the case can be vectorized.
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End-to-end test for #71517, testing IndVars/LoopVectorize interaction
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We are replacing a narrow IV increment with a wider one. If the original (narrow) increment did not wrap, the wider one should not wrap either. Set the flags to be the union of both wide increment and original increment; this ensures we preserve flags SCEV could infer for the wider increment. Fixes llvm#71517.
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#80446) We are replacing a narrow IV increment with a wider one. If the original (narrow) increment did not wrap, the wider one should not wrap either. Set the flags to be the union of both wide increment and original increment; this ensures we preserve flags SCEV could infer for the wider increment. Fixes #71517.
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We are not vectorising kernel s172 from TSVS and are 3x behind compared to GCC as a result. Compile this input with
-O3 -ffast-math -mcpu=neoverse-v2
:Clang's codegen:
GCC's codegen:
See also:
https://godbolt.org/z/W8eEPKqET
TODO: root cause analysis.
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