Skip to content

AArch64 fails with "Don't know how to custom expand this" with illegal f16 #74402

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
arsenm opened this issue Dec 5, 2023 · 4 comments
Open
Assignees

Comments

@arsenm
Copy link
Contributor

arsenm commented Dec 5, 2023

; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=-fp-armv8 < %s

define half @f16_return(float %arg) {
  %fptrunc = fptrunc float %arg to half
  ret half %fptrunc
}

Don't know how to custom expand this
UNREACHABLE executed at /Users/matt/src/llvm-project/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:24529!

@llvmbot
Copy link
Member

llvmbot commented Dec 5, 2023

@llvm/issue-subscribers-backend-aarch64

Author: Matt Arsenault (arsenm)

``` ; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=-fp-armv8 < %s

define half @f16_return(float %arg) {
%fptrunc = fptrunc float %arg to half
ret half %fptrunc
}


Don't know how to custom expand this
UNREACHABLE executed at /Users/matt/src/llvm-project/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:24529!
</details>

@sjoerdmeijer
Copy link
Collaborator

I don't mind taking a look at this. But I was wondering whether you managed to generate this IR from source code, or what your use case is?

The problem is in -mattr=-fp-armv8, where you specify not to have FP support. I will need to remind myself and take a look, but I don't think that is a valid architecture combination. Thus, I also don't know what the solution should be in terms of instructions to do this convert, but I will have a look to remind myself.

@ostannard
Copy link
Collaborator

AArch64 without FP is a valid combination for v8-R, see #74460.

LLVM currently emits calls to the GCC soft-float functions documented at https://gcc.gnu.org/onlinedocs/gccint/Soft-float-library-routines.html, but there isn't any mention of half-precision on that page. It looks like we do have the right function for this in compiler-rt, under the names __extendhfsf2 and __gnu_h2f_ieee: https://github.com/llvm/llvm-project/blob/main/compiler-rt/lib/builtins/extendhfsf2.c. I don't know if these names are documented anywhere though.

@arsenm
Copy link
Contributor Author

arsenm commented Dec 6, 2023

I don't mind taking a look at this. But I was wondering whether you managed to generate this IR from source code, or what your use case is?

I didn't have a real use case, I was just looking for tests for half promotion legalization for a target with a more stable ABI

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Projects
None yet
Development

No branches or pull requests

4 participants