Search results

PPC: Replace PointerLikeRegClass with RegClassByHwMode

backend:AMDGPU

backend:PowerPC

backend:SystemZ

llvm:codegen

llvm:globalisel

llvm:mcMachine (object) codeMachine (object) code

llvm:SelectionDAGSelectionDAGISel as wellSelectionDAGISel as well

tablegen

Status: Open (in progress).

llvm/llvm-projectnumber 158777

#158777 In llvm/llvm-project;

· arsenm opened on Sep 16, 2025

[TableGen, CodeGen, CHERI] Add support for the cPTR wildcard value type.

cheriRelated to CHERI supportRelated to CHERI support

llvm:globalisel

llvm:SelectionDAGSelectionDAGISel as wellSelectionDAGISel as well

tablegen

Status: Open (in progress).

llvm/llvm-projectnumber 158426

#158426 In llvm/llvm-project;

· resistor opened on Sep 13, 2025

[IntrinsicEmitter] Make AttributesMap PackedID type-adaptive

tablegen

Status: Open (in progress).

llvm/llvm-projectnumber 158383

#158383 In llvm/llvm-project;

· elvinw-intel opened on Sep 12, 2025

X86: Switch to RegClassByHwMode

backend:AMDGPU

backend:SystemZ

backend:X86

llvm:codegen

llvm:globalisel

llvm:mcMachine (object) codeMachine (object) code

llvm:SelectionDAGSelectionDAGISel as wellSelectionDAGISel as well

tablegen

Status: Open (in progress).

llvm/llvm-projectnumber 158274

#158274 In llvm/llvm-project;

· arsenm opened on Sep 12, 2025

Mips: Switch to RegClassByHwMode

backend:AMDGPU

backend:MIPS

backend:SystemZ

llvm:codegen

llvm:globalisel

llvm:mcMachine (object) codeMachine (object) code

llvm:SelectionDAGSelectionDAGISel as wellSelectionDAGISel as well

tablegen

Status: Open (in progress).

llvm/llvm-projectnumber 158273

#158273 In llvm/llvm-project;

· arsenm opened on Sep 12, 2025

AMDGPU: Use RegClassByHwMode to manage operand VGPR operand constraints

backend:AMDGPU

backend:SystemZ

llvm:codegen

llvm:globalisel

llvm:mcMachine (object) codeMachine (object) code

llvm:SelectionDAGSelectionDAGISel as wellSelectionDAGISel as well

tablegen

Status: Open (in progress).

llvm/llvm-projectnumber 158272

#158272 In llvm/llvm-project;

· arsenm opened on Sep 12, 2025

CodeGen: Add RegisterClass by HwMode

backend:AMDGPU

backend:SystemZ

llvm:codegen

llvm:globalisel

llvm:mcMachine (object) codeMachine (object) code

llvm:SelectionDAGSelectionDAGISel as wellSelectionDAGISel as well

tablegen

Status: Open (in progress).

llvm/llvm-projectnumber 158269

#158269 In llvm/llvm-project;

· arsenm opened on Sep 12, 2025

CodeGen: Remove TRI arguments from stack load/store hooks

backend:AArch64

backend:AMDGPU

backend:ARC

backend:ARM

backend:CSKY

backend:DirectX

backend:Hexagon

backend:Lanai

backend:loongarch

backend:MIPS

backend:MSP430

backend:NVPTX

backend:PowerPC

backend:RISC-V

backend:Sparc

backend:SPIR-V

backend:SystemZ

backend:WebAssembly

backend:X86

backend:Xtensa

Status: Open (in progress).

llvm/llvm-projectnumber 158240

#158240 In llvm/llvm-project;

· arsenm opened on Sep 12, 2025

CodeGen: Remove TRI argument from reMaterialize

backend:AArch64

backend:AMDGPU

backend:ARC

backend:ARM

backend:CSKY

backend:DirectX

backend:Hexagon

backend:Lanai

backend:loongarch

backend:MIPS

backend:MSP430

backend:NVPTX

backend:PowerPC

backend:RISC-V

backend:Sparc

backend:SPIR-V

backend:SystemZ

backend:WebAssembly

backend:X86

backend:Xtensa

Status: Open (in progress).

llvm/llvm-projectnumber 158229

#158229 In llvm/llvm-project;

· arsenm opened on Sep 12, 2025

ARM: Remove TRI argument from AddDReg

backend:AArch64

backend:AMDGPU

backend:ARC

backend:ARM

backend:CSKY

backend:DirectX

backend:Hexagon

backend:Lanai

backend:loongarch

backend:MIPS

backend:MSP430

backend:NVPTX

backend:PowerPC

backend:RISC-V

backend:Sparc

backend:SPIR-V

backend:SystemZ

backend:WebAssembly

backend:X86

backend:Xtensa

Status: Open (in progress).

llvm/llvm-projectnumber 158228

#158228 In llvm/llvm-project;

· arsenm opened on Sep 12, 2025

CodeGen: Remove TRI argument from getRegClass

backend:AArch64

backend:AMDGPU

backend:ARC

backend:ARM

backend:CSKY

backend:DirectX

backend:Hexagon

backend:Lanai

backend:loongarch

backend:MIPS

backend:MSP430

backend:NVPTX

backend:PowerPC

backend:RISC-V

backend:Sparc

backend:SPIR-V

backend:SystemZ

backend:WebAssembly

backend:X86

backend:Xtensa

Status: Open (in progress).

llvm/llvm-projectnumber 158225

#158225 In llvm/llvm-project;

· arsenm opened on Sep 12, 2025

CodeGen: Keep reference to TargetRegisterInfo in TargetInstrInfo

backend:AArch64

backend:AMDGPU

backend:ARC

backend:ARM

backend:CSKY

backend:DirectX

backend:Hexagon

backend:Lanai

backend:loongarch

backend:MIPS

backend:MSP430

backend:NVPTX

backend:PowerPC

backend:RISC-V

backend:Sparc

backend:SPIR-V

backend:SystemZ

backend:WebAssembly

backend:X86

backend:Xtensa

Status: Open (in progress).

llvm/llvm-projectnumber 158224

#158224 In llvm/llvm-project;

· arsenm opened on Sep 12, 2025

TableGen asserts on invalid cast

crash-on-invalid

tablegen

Status: Open.

Bug

#157619 In llvm/llvm-project;

· arsenm opened on Sep 9, 2025

[Inclusive Language] migrate "sanity" checks to "soundness" checks

backend:AArch64

backend:AMDGPU

backend:ARM

backend:Hexagon

backend:m68k

backend:MIPS

backend:RISC-V

backend:Sparc

backend:SPIR-V

backend:X86

BOLT

clangClang issues not falling into any other categoryClang issues not falling into any other category

clang-tidy

clang-tools-extra

clang:codegenIR generation bugs: mangling, exceptions, etc.IR generation bugs: mangling, exceptions, etc.

clang:driver'clang' and 'clang++' user-facing binaries. Not 'clang-cl''clang' and 'clang++' user-facing binaries. Not 'clang-cl'

clang:frontendLanguage frontend issues, e.g. anything involving "Sema"Language frontend issues, e.g. anything involving "Sema"

clang:static analyzer

clangd

cmakeBuild system in general and CMake in particularBuild system in general and CMake in particular

Status: Open (in progress).

llvm/llvm-projectnumber 156995

#156995 In llvm/llvm-project;

· vanvoorden opened on Sep 5, 2025

[TableGen][DecoderEmitter] Rework table construction/emission

llvm:mcMachine (object) codeMachine (object) code

tablegen

Status: Open (in progress).

llvm/llvm-projectnumber 155889

#155889 In llvm/llvm-project;

· s-barannikov opened on Aug 28, 2025

[Draft][LLVM] Refine MemoryEffect handling for target-specific intrinsics

backend:AArch64

clangClang issues not falling into any other categoryClang issues not falling into any other category

llvm:analysisIncludes value tracking, cost tables and constant foldingIncludes value tracking, cost tables and constant folding

llvm:ir

llvm:support

llvm:transforms

tablegen

Status: Draft (not ready).

llvm/llvm-projectnumber 155590

#155590 In llvm/llvm-project;

· CarolineConcatto opened on Aug 27, 2025

[GlobalISel][LLT] Introduce FPInfo for LLT (Enable bfloat, ppc128float and others in GlobalISel)

backend:AArch64

backend:AMDGPU

llvm:codegen

llvm:globalisel

llvm:SelectionDAGSelectionDAGISel as wellSelectionDAGISel as well

tablegen

Status: Open (in progress).

llvm/llvm-projectnumber 155107

#155107 In llvm/llvm-project;

· DenisGZM opened on Aug 23, 2025

[TableGen] Cyclic super classes cause stack overflows

tablegen

Status: Open.

#155103 In llvm/llvm-project;

· zero9178 opened on Aug 23, 2025

[NFC][LLVM] Update attributes for FP8 instructions using new target memory locations

backend:AArch64

clangClang issues not falling into any other categoryClang issues not falling into any other category

llvm:ir

llvm:support

llvm:transforms

tablegen

Status: Open (in progress).

llvm/llvm-projectnumber 154144

#154144 In llvm/llvm-project;

· CarolineConcatto opened on Aug 18, 2025

[LLVM]Add read and write inaccessible memory metadata

llvm:ir

llvm:support

llvm:transforms

tablegen

Status: Open (in progress).

llvm/llvm-projectnumber 154141

#154141 In llvm/llvm-project;

· CarolineConcatto opened on Aug 18, 2025

Documenting the usage of TableGen records and expected behaviors in each TableGen backend

documentation

tablegen

Status: Open.

#152339 In llvm/llvm-project;

· mshockwave opened on Aug 6, 2025

TableGen compiler points to non-existent line when source is just a single #ifdef (and crashes on one platform)

tablegen

Status: Open.

#151476 In llvm/llvm-project;

· DavidSpickett opened on Jul 31, 2025

[TableGen] ASAN reports use-after-poison in StringInit::get, when used with BumpPtrAllocator

tablegen

Status: Open.

#151430 In llvm/llvm-project;

· chanha-park opened on Jul 31, 2025

TableGen backends as plugins

enhancementImproving things as opposed to bug fixing, e.g. new or missing featureImproving things as opposed to bug fixing, e.g. new or missing feature

tablegen

Status: Open.

Feature

#151299 In llvm/llvm-project;

· DavidSpickett opened on Jul 30, 2025

[TableGen] Update LLVM TableGen documentation with some of the common errors and its possible meaning

documentation

tablegen

Status: Open.

#151179 In llvm/llvm-project;

· pchaudhuri-nv opened on Jul 29, 2025