Mips: Switch to RegClassByHwMode #158273

arsenm · 2025-09-12T11:15:10Z

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arsenm · 2025-09-12T11:15:33Z

Mips: Switch to RegClassByHwMode #158273 👈 (View in Graphite)
CodeGen: Add RegisterClass by HwMode #158269 : 4 other dependent PRs (#158271 , #158272 , #158274 and 1 other)
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llvmbot · 2025-09-12T11:15:41Z

@llvm/pr-subscribers-backend-mips
@llvm/pr-subscribers-llvm-mc
@llvm/pr-subscribers-tablegen
@llvm/pr-subscribers-backend-amdgpu

@llvm/pr-subscribers-llvm-selectiondag

Author: Matt Arsenault (arsenm)

Changes

Full diff: https://github.com/llvm/llvm-project/pull/158273.diff

7 Files Affected:

(modified) llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp (+7-2)
(modified) llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp (+24)
(modified) llvm/lib/Target/Mips/MicroMipsInstrInfo.td (+3-9)
(modified) llvm/lib/Target/Mips/Mips.td (+15)
(modified) llvm/lib/Target/Mips/MipsInstrInfo.td (+9-11)
(modified) llvm/lib/Target/Mips/MipsRegisterInfo.cpp (+2-14)
(modified) llvm/lib/Target/Mips/MipsRegisterInfo.td (+16)

diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
index 8a5cb517c94c5..a8fd010c58ac8 100644
--- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
+++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
@@ -3706,7 +3706,9 @@ void MipsAsmParser::expandMem16Inst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
   MCRegister TmpReg = DstReg;
 
   const MCInstrDesc &Desc = MII.get(OpCode);
-  int16_t DstRegClass = Desc.operands()[StartOp].RegClass;
+  int16_t DstRegClass =
+      MII.getOpRegClassID(Desc.operands()[StartOp],
+                          STI->getHwMode(MCSubtargetInfo::HwMode_RegClass));
   unsigned DstRegClassID =
       getContext().getRegisterInfo()->getRegClass(DstRegClass).getID();
   bool IsGPR = (DstRegClassID == Mips::GPR32RegClassID) ||
@@ -3834,7 +3836,10 @@ void MipsAsmParser::expandMem9Inst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
   MCRegister TmpReg = DstReg;
 
   const MCInstrDesc &Desc = MII.get(OpCode);
-  int16_t DstRegClass = Desc.operands()[StartOp].RegClass;
+  int16_t DstRegClass =
+      MII.getOpRegClassID(Desc.operands()[StartOp],
+                          STI->getHwMode(MCSubtargetInfo::HwMode_RegClass));
+
   unsigned DstRegClassID =
       getContext().getRegisterInfo()->getRegClass(DstRegClass).getID();
   bool IsGPR = (DstRegClassID == Mips::GPR32RegClassID) ||
diff --git a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
index fa6cc0e3f0187..d569eda328ef0 100644
--- a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
+++ b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
@@ -916,6 +916,30 @@ DecodeGPRMM16MovePRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
   return MCDisassembler::Success;
 }
 
+static DecodeStatus DecodeGP32RegisterClass(MCInst &Inst, unsigned RegNo,
+                                            uint64_t Address,
+                                            const MCDisassembler *Decoder) {
+  llvm_unreachable("this is unused");
+}
+
+static DecodeStatus DecodeGP64RegisterClass(MCInst &Inst, unsigned RegNo,
+                                            uint64_t Address,
+                                            const MCDisassembler *Decoder) {
+  llvm_unreachable("this is unused");
+}
+
+static DecodeStatus DecodeSP32RegisterClass(MCInst &Inst, unsigned RegNo,
+                                            uint64_t Address,
+                                            const MCDisassembler *Decoder) {
+  llvm_unreachable("this is unused");
+}
+
+static DecodeStatus DecodeSP64RegisterClass(MCInst &Inst, unsigned RegNo,
+                                            uint64_t Address,
+                                            const MCDisassembler *Decoder) {
+  llvm_unreachable("this is unused");
+}
+
 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
                                              uint64_t Address,
                                              const MCDisassembler *Decoder) {
diff --git a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td
index b3fd8f422f429..b44bf1391b73e 100644
--- a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td
+++ b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td
@@ -57,12 +57,6 @@ def MicroMipsMemGPRMM16AsmOperand : AsmOperandClass {
   let PredicateMethod = "isMemWithGRPMM16Base";
 }
 
-// Define the classes of pointers used by microMIPS.
-// The numbers must match those in MipsRegisterInfo::MipsPtrClass.
-def ptr_gpr16mm_rc : PointerLikeRegClass<1>;
-def ptr_sp_rc : PointerLikeRegClass<2>;
-def ptr_gp_rc : PointerLikeRegClass<3>;
-
 class mem_mm_4_generic : Operand<i32> {
   let PrintMethod = "printMemOperand";
   let MIOperandInfo = (ops ptr_gpr16mm_rc, simm4);
@@ -114,7 +108,7 @@ def mem_mm_gp_simm7_lsl2 : Operand<i32> {
 
 def mem_mm_9 : Operand<i32> {
   let PrintMethod = "printMemOperand";
-  let MIOperandInfo = (ops ptr_rc, simm9);
+  let MIOperandInfo = (ops mips_ptr_rc, simm9);
   let EncoderMethod = "getMemEncodingMMImm9";
   let ParserMatchClass = MipsMemSimmAsmOperand<9>;
   let OperandType = "OPERAND_MEMORY";
@@ -130,7 +124,7 @@ def mem_mm_11 : Operand<i32> {
 
 def mem_mm_12 : Operand<i32> {
   let PrintMethod = "printMemOperand";
-  let MIOperandInfo = (ops ptr_rc, simm12);
+  let MIOperandInfo = (ops mips_ptr_rc, simm12);
   let EncoderMethod = "getMemEncodingMMImm12";
   let ParserMatchClass = MipsMemAsmOperand;
   let OperandType = "OPERAND_MEMORY";
@@ -138,7 +132,7 @@ def mem_mm_12 : Operand<i32> {
 
 def mem_mm_16 : Operand<i32> {
   let PrintMethod = "printMemOperand";
-  let MIOperandInfo = (ops ptr_rc, simm16);
+  let MIOperandInfo = (ops mips_ptr_rc, simm16);
   let EncoderMethod = "getMemEncodingMMImm16";
   let DecoderMethod = "DecodeMemMMImm16";
   let ParserMatchClass = MipsMemSimmAsmOperand<16>;
diff --git a/llvm/lib/Target/Mips/Mips.td b/llvm/lib/Target/Mips/Mips.td
index b346ba95f5984..bfde7740ba011 100644
--- a/llvm/lib/Target/Mips/Mips.td
+++ b/llvm/lib/Target/Mips/Mips.td
@@ -211,6 +211,21 @@ def FeatureUseIndirectJumpsHazard : SubtargetFeature<"use-indirect-jump-hazard",
 def FeatureStrictAlign
     : SubtargetFeature<"strict-align", "StrictAlign", "true",
                        "Disable unaligned load store for r6">;
+//===----------------------------------------------------------------------===//
+// Mips Instruction Predicate Definitions.
+//===----------------------------------------------------------------------===//
+
+def IsPTR64bit    :   Predicate<"Subtarget->isABI_N64()">,
+                      AssemblerPredicate<(all_of FeaturePTR64Bit)>;
+def IsPTR32bit    :   Predicate<"!Subtarget->isABI_N64()">,
+                      AssemblerPredicate<(all_of (not FeaturePTR64Bit))>;
+
+//===----------------------------------------------------------------------===//
+// HwModes
+//===----------------------------------------------------------------------===//
+
+defvar MIPS32 = DefaultMode;
+def MIPS64 : HwMode<[IsPTR64bit]>;
 
 //===----------------------------------------------------------------------===//
 // Register File, Calling Conv, Instruction Descriptions
diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td
index a124e84e9ca5f..eff80e59c64c9 100644
--- a/llvm/lib/Target/Mips/MipsInstrInfo.td
+++ b/llvm/lib/Target/Mips/MipsInstrInfo.td
@@ -156,6 +156,8 @@ def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
 //===----------------------------------------------------------------------===//
 // Mips Instruction Predicate Definitions.
 //===----------------------------------------------------------------------===//
+// FIXME: Move to Mips.td
+
 def HasMips2     :    Predicate<"Subtarget->hasMips2()">,
                       AssemblerPredicate<(all_of FeatureMips2)>;
 def HasMips3_32  :    Predicate<"Subtarget->hasMips3_32()">,
@@ -188,10 +190,6 @@ def IsGP64bit    :    Predicate<"Subtarget->isGP64bit()">,
                       AssemblerPredicate<(all_of FeatureGP64Bit)>;
 def IsGP32bit    :    Predicate<"!Subtarget->isGP64bit()">,
                       AssemblerPredicate<(all_of (not FeatureGP64Bit))>;
-def IsPTR64bit    :   Predicate<"Subtarget->isABI_N64()">,
-                      AssemblerPredicate<(all_of FeaturePTR64Bit)>;
-def IsPTR32bit    :   Predicate<"!Subtarget->isABI_N64()">,
-                      AssemblerPredicate<(all_of (not FeaturePTR64Bit))>;
 def HasMips64    :    Predicate<"Subtarget->hasMips64()">,
                       AssemblerPredicate<(all_of FeatureMips64)>;
 def NotMips64    :    Predicate<"!Subtarget->hasMips64()">,
@@ -1125,7 +1123,7 @@ def InvertedImOperand64 : Operand<i64> {
 
 class mem_generic : Operand<iPTR> {
   let PrintMethod = "printMemOperand";
-  let MIOperandInfo = (ops ptr_rc, simm16);
+  let MIOperandInfo = (ops mips_ptr_rc, simm16);
   let EncoderMethod = "getMemEncoding";
   let ParserMatchClass = MipsMemAsmOperand;
   let OperandType = "OPERAND_MEMORY";
@@ -1136,7 +1134,7 @@ def mem : mem_generic;
 
 // MSA specific address operand
 def mem_msa : mem_generic {
-  let MIOperandInfo = (ops ptr_rc, simm10);
+  let MIOperandInfo = (ops mips_ptr_rc, simm10);
   let EncoderMethod = "getMSAMemEncoding";
 }
 
@@ -1145,7 +1143,7 @@ def simm12 : Operand<i32> {
 }
 
 def mem_simm9_exp : mem_generic {
-  let MIOperandInfo = (ops ptr_rc, simm9);
+  let MIOperandInfo = (ops mips_ptr_rc, simm9);
   let ParserMatchClass = MipsMemSimmPtrAsmOperand;
   let OperandNamespace = "MipsII";
   let OperandType = "OPERAND_MEM_SIMM9";
@@ -1153,13 +1151,13 @@ def mem_simm9_exp : mem_generic {
 
 foreach I = {9, 10, 11, 12, 16} in
   def mem_simm # I : mem_generic {
-    let MIOperandInfo = (ops ptr_rc, !cast<Operand>("simm" # I));
+    let MIOperandInfo = (ops mips_ptr_rc, !cast<Operand>("simm" # I));
     let ParserMatchClass = MipsMemSimmAsmOperand<I>;
   }
 
 foreach I = {1, 2, 3} in
   def mem_simm10_lsl # I : mem_generic {
-    let MIOperandInfo = (ops ptr_rc, !cast<Operand>("simm10_lsl" # I));
+    let MIOperandInfo = (ops mips_ptr_rc, !cast<Operand>("simm10_lsl" # I));
     let EncoderMethod = "getMemEncoding<" # I  # ">";
     let ParserMatchClass = MipsMemSimmAsmOperand<10, I>;
   }
@@ -1170,13 +1168,13 @@ def mem_simmptr : mem_generic {
 
 def mem_ea : Operand<iPTR> {
   let PrintMethod = "printMemOperandEA";
-  let MIOperandInfo = (ops ptr_rc, simm16);
+  let MIOperandInfo = (ops mips_ptr_rc, simm16);
   let EncoderMethod = "getMemEncoding";
   let OperandType = "OPERAND_MEMORY";
 }
 
 def PtrRC : Operand<iPTR> {
-  let MIOperandInfo = (ops ptr_rc);
+  let MIOperandInfo = (ops mips_ptr_rc);
   let DecoderMethod = "DecodePtrRegisterClass";
   let ParserMatchClass = GPR32AsmOperand;
 }
diff --git a/llvm/lib/Target/Mips/MipsRegisterInfo.cpp b/llvm/lib/Target/Mips/MipsRegisterInfo.cpp
index 4d105bddd4d9c..6f8d6764e77b8 100644
--- a/llvm/lib/Target/Mips/MipsRegisterInfo.cpp
+++ b/llvm/lib/Target/Mips/MipsRegisterInfo.cpp
@@ -46,20 +46,8 @@ unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; }
 
 const TargetRegisterClass *
 MipsRegisterInfo::getPointerRegClass(unsigned Kind) const {
-  MipsPtrClass PtrClassKind = static_cast<MipsPtrClass>(Kind);
-
-  switch (PtrClassKind) {
-  case MipsPtrClass::Default:
-    return ArePtrs64bit ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
-  case MipsPtrClass::GPR16MM:
-    return &Mips::GPRMM16RegClass;
-  case MipsPtrClass::StackPointer:
-    return ArePtrs64bit ? &Mips::SP64RegClass : &Mips::SP32RegClass;
-  case MipsPtrClass::GlobalPointer:
-    return ArePtrs64bit ? &Mips::GP64RegClass : &Mips::GP32RegClass;
-  }
-
-  llvm_unreachable("Unknown pointer kind");
+  assert(Kind == 0 && "this should only be used for default case");
+  return ArePtrs64bit ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
 }
 
 unsigned
diff --git a/llvm/lib/Target/Mips/MipsRegisterInfo.td b/llvm/lib/Target/Mips/MipsRegisterInfo.td
index 237ccdc5cc967..80ff119be37d5 100644
--- a/llvm/lib/Target/Mips/MipsRegisterInfo.td
+++ b/llvm/lib/Target/Mips/MipsRegisterInfo.td
@@ -758,3 +758,19 @@ def MSA128DOpnd : RegisterOperand<MSA128D> {
 def MSA128CROpnd : RegisterOperand<MSACtrl> {
   let ParserMatchClass = MSACtrlAsmOperand;
 }
+
+def mips_ptr_rc : RegClassByHwMode<
+  [MIPS32, MIPS64],
+  [GPR32, GPR64]>;
+
+def ptr_gpr16mm_rc : RegClassByHwMode<
+  [MIPS32, MIPS64],
+  [GPRMM16, GPRMM16]>; // FIXME: Why even use this if it's just a constant
+
+def ptr_sp_rc : RegClassByHwMode<
+  [MIPS32, MIPS64],
+  [SP32, SP64]>;
+
+def ptr_gp_rc : RegClassByHwMode<
+  [MIPS32, MIPS64],
+  [GP32, GP64]>;

llvm/lib/Target/Mips/Mips.td

llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp

s-barannikov

LGTM

llvm/lib/Target/Mips/MipsRegisterInfo.cpp

arsenm added backend:AMDGPU backend:SystemZ llvm:codegen llvm:globalisel llvm:mc Machine (object) code llvm:SelectionDAG SelectionDAGISel as well tablegen labels Sep 12, 2025 — with Graphite App

arsenm requested review from asb, cdevadas, jayfoad, jurahul, KanRobert, kparzysz, preames, qcolombet, rampitec, RKSimon, s-barannikov, shiltian, Sisyph and topperc September 12, 2025 11:15

This was referenced Sep 12, 2025

SPARC: Use RegClassByHwMode instead of PointerLikeRegClass #158271

Merged

CodeGen: Add RegisterClass by HwMode #158269

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arsenm mentioned this pull request Sep 12, 2025

AMDGPU: Use RegClassByHwMode to manage operand VGPR operand constraints #158272

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arsenm marked this pull request as ready for review September 12, 2025 11:15

llvmbot added the backend:MIPS label Sep 12, 2025

This was referenced Sep 12, 2025

X86: Switch to RegClassByHwMode #158274

Merged

AMDGPU: Stop using aligned VGPR classes for addRegisterClass #158278

Open

arsenm force-pushed the users/arsenm/mips/use-RegClassByHwMode branch from f139637 to cf6589f Compare September 15, 2025 11:40

arsenm force-pushed the users/arsenm/codegen/targetinstrinfo-add-regclass-by-hwmode branch from ba508eb to b0954df Compare September 15, 2025 11:40

arsenm force-pushed the users/arsenm/mips/use-RegClassByHwMode branch from cf6589f to cc9b01e Compare September 16, 2025 04:51

arsenm mentioned this pull request Sep 16, 2025

PPC: Replace PointerLikeRegClass with RegClassByHwMode #158777

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arsenm force-pushed the users/arsenm/codegen/targetinstrinfo-add-regclass-by-hwmode branch from 480926a to bdfdc33 Compare September 17, 2025 15:22

arsenm force-pushed the users/arsenm/mips/use-RegClassByHwMode branch 2 times, most recently from 6d6e9fd to 6fbe887 Compare September 18, 2025 00:23

s-barannikov reviewed Sep 19, 2025

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arsenm force-pushed the users/arsenm/codegen/targetinstrinfo-add-regclass-by-hwmode branch from da6fc27 to 8bfcdcc Compare September 19, 2025 06:01

arsenm force-pushed the users/arsenm/mips/use-RegClassByHwMode branch from 6fbe887 to f0d6719 Compare September 19, 2025 06:01

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Base automatically changed from users/arsenm/codegen/targetinstrinfo-add-regclass-by-hwmode to main September 19, 2025 11:08

arsenm added 4 commits September 19, 2025 21:54

Mips: Switch to RegClassByHwMode

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Add blank line before comment

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Add disassembler comment

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Remove enum

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arsenm force-pushed the users/arsenm/mips/use-RegClassByHwMode branch from c14bc7a to a29b2f7 Compare September 19, 2025 13:14

arsenm enabled auto-merge (squash) September 19, 2025 13:16

arsenm merged commit 084872a into main Sep 19, 2025
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arsenm deleted the users/arsenm/mips/use-RegClassByHwMode branch September 19, 2025 13:50

SeongjaeP pushed a commit to SeongjaeP/llvm-project that referenced this pull request Sep 23, 2025

Mips: Switch to RegClassByHwMode (llvm#158273)

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YixingZhang007 pushed a commit to YixingZhang007/llvm-project that referenced this pull request Sep 27, 2025

Mips: Switch to RegClassByHwMode (llvm#158273)

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