Skip to content

[AMDGPU] Use a generic printer for NamedIntOperands. #100399

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 1 commit into from
Jul 29, 2024
Merged

[AMDGPU] Use a generic printer for NamedIntOperands. #100399

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
100 changes: 7 additions & 93 deletions llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -119,20 +119,6 @@ void AMDGPUInstPrinter::printFlatOffset(const MCInst *MI, unsigned OpNo,
}
}

void AMDGPUInstPrinter::printOffset0(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI,
raw_ostream &O) {
if (int64_t Offset = MI->getOperand(OpNo).getImm())
O << " offset0:" << formatDec(Offset);
}

void AMDGPUInstPrinter::printOffset1(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI,
raw_ostream &O) {
if (int64_t Offset = MI->getOperand(OpNo).getImm())
O << " offset1:" << formatDec(Offset);
}

void AMDGPUInstPrinter::printSMRDOffset8(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI,
raw_ostream &O) {
Expand All @@ -145,13 +131,6 @@ void AMDGPUInstPrinter::printSMEMOffset(const MCInst *MI, unsigned OpNo,
O << formatHex(MI->getOperand(OpNo).getImm());
}

void AMDGPUInstPrinter::printSMEMOffsetMod(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI,
raw_ostream &O) {
O << " offset:";
printSMEMOffset(MI, OpNo, STI, O);
}

void AMDGPUInstPrinter::printSMRDLiteralOffset(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI,
raw_ostream &O) {
Expand Down Expand Up @@ -269,14 +248,6 @@ void AMDGPUInstPrinter::printScope(int64_t Scope, raw_ostream &O) {
return;
}

void AMDGPUInstPrinter::printDMask(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O) {
if (MI->getOperand(OpNo).getImm()) {
O << " dmask:";
printU16ImmOperand(MI, OpNo, STI, O);
}
}

void AMDGPUInstPrinter::printDim(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O) {
unsigned Dim = MI->getOperand(OpNo).getImm();
Expand Down Expand Up @@ -678,26 +649,6 @@ void AMDGPUInstPrinter::printBLGP(const MCInst *MI, unsigned OpNo,
O << " blgp:" << Imm;
}

void AMDGPUInstPrinter::printCBSZ(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI,
raw_ostream &O) {
unsigned Imm = MI->getOperand(OpNo).getImm();
if (!Imm)
return;

O << " cbsz:" << Imm;
}

void AMDGPUInstPrinter::printABID(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI,
raw_ostream &O) {
unsigned Imm = MI->getOperand(OpNo).getImm();
if (!Imm)
return;

O << " abid:" << Imm;
}

void AMDGPUInstPrinter::printDefaultVccOperand(bool FirstOperand,
const MCSubtargetInfo &STI,
raw_ostream &O) {
Expand All @@ -711,30 +662,6 @@ void AMDGPUInstPrinter::printDefaultVccOperand(bool FirstOperand,
O << ", ";
}

void AMDGPUInstPrinter::printWaitVDST(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI,
raw_ostream &O) {
O << " wait_vdst:" << formatDec(MI->getOperand(OpNo).getImm());
}

void AMDGPUInstPrinter::printWaitVAVDst(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI,
raw_ostream &O) {
O << " wait_va_vdst:" << formatDec(MI->getOperand(OpNo).getImm());
}

void AMDGPUInstPrinter::printWaitVMVSrc(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI,
raw_ostream &O) {
O << " wait_vm_vsrc:" << formatDec(MI->getOperand(OpNo).getImm());
}

void AMDGPUInstPrinter::printWaitEXP(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI,
raw_ostream &O) {
O << " wait_exp:" << formatDec(MI->getOperand(OpNo).getImm());
}

bool AMDGPUInstPrinter::needsImpliedVcc(const MCInstrDesc &Desc,
unsigned OpNo) const {
return OpNo == 0 && (Desc.TSFlags & SIInstrFlags::DPP) &&
Expand Down Expand Up @@ -1127,18 +1054,6 @@ void AMDGPUInstPrinter::printDPPCtrl(const MCInst *MI, unsigned OpNo,
}
}

void AMDGPUInstPrinter::printDppRowMask(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI,
raw_ostream &O) {
O << " row_mask:" << formatHex(MI->getOperand(OpNo).getImm());
}

void AMDGPUInstPrinter::printDppBankMask(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI,
raw_ostream &O) {
O << " bank_mask:" << formatHex(MI->getOperand(OpNo).getImm());
}

void AMDGPUInstPrinter::printDppBoundCtrl(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI,
raw_ostream &O) {
Expand Down Expand Up @@ -1782,14 +1697,13 @@ void AMDGPUInstPrinter::printEndpgm(const MCInst *MI, unsigned OpNo,
O << ' ' << formatDec(Imm);
}

void AMDGPUInstPrinter::printByteSel(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI,
raw_ostream &O) {
uint8_t Imm = MI->getOperand(OpNo).getImm();
if (!Imm)
return;

O << " byte_sel:" << formatDec(Imm);
void AMDGPUInstPrinter::printNamedInt(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI,
raw_ostream &O, StringRef Prefix,
bool PrintInHex, bool AlwaysPrint) {
int64_t V = MI->getOperand(OpNo).getImm();
if (AlwaysPrint || V != 0)
O << ' ' << Prefix << ':' << (PrintInHex ? formatHex(V) : formatDec(V));
}

#include "AMDGPUGenAsmWriter.inc"
29 changes: 3 additions & 26 deletions llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -48,24 +48,16 @@ class AMDGPUInstPrinter : public MCInstPrinter {
void printFlatOffset(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
raw_ostream &O);

void printOffset0(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
raw_ostream &O);
void printOffset1(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
raw_ostream &O);
void printSMRDOffset8(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O);
void printSMEMOffset(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O);
void printSMEMOffsetMod(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O);
void printSMRDLiteralOffset(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O);
void printCPol(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O);
void printTH(const MCInst *MI, int64_t TH, int64_t Scope, raw_ostream &O);
void printScope(int64_t Scope, raw_ostream &O);
void printDMask(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
raw_ostream &O);
void printDim(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
raw_ostream &O);
void printR128A16(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
Expand Down Expand Up @@ -110,10 +102,6 @@ class AMDGPUInstPrinter : public MCInstPrinter {
raw_ostream &O);
void printDPPCtrl(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
raw_ostream &O);
void printDppRowMask(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O);
void printDppBankMask(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O);
void printDppBoundCtrl(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O);
void printDppFI(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
Expand Down Expand Up @@ -154,21 +142,9 @@ class AMDGPUInstPrinter : public MCInstPrinter {
const MCSubtargetInfo &STI, raw_ostream &O);
void printBLGP(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
raw_ostream &O);
void printCBSZ(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
raw_ostream &O);
void printABID(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
raw_ostream &O);
bool needsImpliedVcc(const MCInstrDesc &Desc, unsigned OpNo) const;
void printDefaultVccOperand(bool FirstOperand, const MCSubtargetInfo &STI,
raw_ostream &O);
void printWaitVDST(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
raw_ostream &O);
void printWaitEXP(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
raw_ostream &O);
void printWaitVAVDst(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O);
void printWaitVMVSrc(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O);

void printExpSrcN(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
raw_ostream &O, unsigned N);
Expand All @@ -182,8 +158,9 @@ class AMDGPUInstPrinter : public MCInstPrinter {
const MCSubtargetInfo &STI, raw_ostream &O);
void printExpTgt(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O);
void printByteSel(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
raw_ostream &O);
void printNamedInt(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O,
StringRef Prefix, bool PrintInHex, bool AlwaysPrint);

public:
static void printIfSet(const MCInst *MI, unsigned OpNo, raw_ostream &O,
Expand Down
23 changes: 20 additions & 3 deletions llvm/lib/Target/AMDGPU/SIInstrInfo.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1015,18 +1015,29 @@ def SDWAVopcDst : BoolRC {
let PrintMethod = "printVOPDst";
}

class NamedIntOperand<ValueType Type, string Prefix, bit Optional = 1,
class NamedIntOperand<ValueType Type, string prefix, bit Optional = 1,
string name = NAME>
: CustomOperand<Type, Optional, name> {
string Prefix = prefix;

let PredicateMethod =
"getPredicate([](const AMDGPUOperand &Op) -> bool { "#
"return Op.isImmTy(AMDGPUOperand::"#ImmTy#"); })";

string Validator = "[](int64_t V) { return true; }";
string ConvertMethod = "[](int64_t &V) { return "#Validator#"(V); }";
let ParserMethod =
"[this](OperandVector &Operands) -> ParseStatus { "#
"return parseIntWithPrefix(\""#Prefix#"\", Operands, "#
"AMDGPUOperand::"#ImmTy#", "#ConvertMethod#"); }";

bit PrintInHex = 0;
bit AlwaysPrint = 0;
let PrintMethod = "[this](const MCInst *MI, unsigned OpNo, "
"const MCSubtargetInfo &STI, raw_ostream &O) { "
"printNamedInt(MI, OpNo, STI, O, \""#Prefix#"\", "#
!if(PrintInHex, "true", "false")#", "#
!if(AlwaysPrint, "true", "false")#"); }";
}

class NamedBitOperand<string Id, string Name = NAME>
Expand Down Expand Up @@ -1065,6 +1076,7 @@ class ArrayOperand0<string Id, string Name = NAME>

let ImmTy = "ImmTyOffset" in
def flat_offset : CustomOperand<i32, 1, "FlatOffset">;
let PrintMethod = "printOffset" in
def Offset : NamedIntOperand<i32, "offset">;
let Validator = "isUInt<8>" in {
def Offset0 : NamedIntOperand<i32, "offset0">;
Expand Down Expand Up @@ -1103,6 +1115,7 @@ def exp_vm : NamedBitOperand<"vm", "ExpVM">;

def FORMAT : CustomOperand<i8>;

let PrintInHex = 1 in
def DMask : NamedIntOperand<i16, "dmask">;

def Dim : CustomOperand<i8, /*optional=*/1>;
Expand All @@ -1123,16 +1136,18 @@ def IndexKey8bit : CustomOperand<i32, 1>;
def dpp8 : CustomOperand<i32, 0, "DPP8">;
def dpp_ctrl : CustomOperand<i32, 0, "DPPCtrl">;

let DefaultValue = "0xf" in {
let DefaultValue = "0xf", PrintInHex = 1, AlwaysPrint = 1 in {
def DppRowMask : NamedIntOperand<i32, "row_mask">;
def DppBankMask : NamedIntOperand<i32, "bank_mask">;
}
def DppBoundCtrl : NamedIntOperand<i1, "bound_ctrl"> {
let ConvertMethod = "[this] (int64_t &BC) -> bool { return convertDppBoundCtrl(BC); }";
let PrintMethod = "printDppBoundCtrl";
}

let DecoderMethod = "decodeDpp8FI" in
let DecoderMethod = "decodeDpp8FI", PrintMethod = "printDppFI" in
def Dpp8FI : NamedIntOperand<i32, "fi", 1, "DppFI">;
let PrintMethod = "printDppFI" in
def Dpp16FI : NamedIntOperand<i32, "fi", 1, "DppFI">;

def blgp : CustomOperand<i32, 1, "BLGP">;
Expand All @@ -1146,6 +1161,7 @@ def hwreg : CustomOperand<i32, 0, "Hwreg">;

def exp_tgt : CustomOperand<i32, 0, "ExpTgt">;

let AlwaysPrint = 1 in {
def WaitVDST : NamedIntOperand<i8, "wait_vdst"> {
let Validator = "isUInt<4>";
}
Expand All @@ -1158,6 +1174,7 @@ def WaitVAVDst : NamedIntOperand<i8, "wait_va_vdst"> {
def WaitVMVSrc : NamedIntOperand<i8, "wait_vm_vsrc"> {
let Validator = "isUInt<1>";
}
} // End AlwaysPrint = 1

def ByteSel : NamedIntOperand<i8, "byte_sel"> {
let Validator = "isUInt<2>";
Expand Down
5 changes: 4 additions & 1 deletion llvm/lib/Target/AMDGPU/SMInstructions.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -11,7 +11,10 @@ def smrd_offset_8 : ImmOperand<i32, "SMRDOffset8", 1>;
let EncoderMethod = "getSMEMOffsetEncoding",
DecoderMethod = "decodeSMEMOffset" in {
def SMEMOffset : ImmOperand<i32, "SMEMOffset", 1>;
def SMEMOffsetMod : NamedIntOperand<i32, "offset", 0>;
def SMEMOffsetMod : NamedIntOperand<i32, "offset", 0> {
let AlwaysPrint = 1;
let PrintInHex = 1;
}
def OptSMEMOffsetMod : NamedIntOperand<i32, "offset"> {
let ImmTy = SMEMOffsetMod.ImmTy;
let PredicateMethod = SMEMOffsetMod.PredicateMethod;
Expand Down
Loading