release/19.x: [Mips] Fix fast isel for i16 bswap. (#103398) #104745
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@dtcxzyw What do you think about merging this PR to the release branch? |
dtcxzyw
approved these changes
Aug 19, 2024
We need to mask the SRL result to 8 bits before ORing in the SLL. This is needed in case bits 23:16 of the input aren't zero. They will have been shifted into bits 15:8. We don't need to AND the result with 0xffff. It's ok if the upper 16 bits of the register are garbage. Fixes llvm#103035. (cherry picked from commit ebe7265)
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@nikic (or anyone else). If you would like to add a note about this fix in the release notes (completely optional). Please reply to this comment with a one or two sentence description of the fix. When you are done, please add the release:note label to this PR. |
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Backport ebe7265
Requested by: @nikic