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[AArch64] Remove redundant COPY from loadRegFromStackSlot #107396

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Merged
merged 1 commit into from
Sep 5, 2024
Merged

[AArch64] Remove redundant COPY from loadRegFromStackSlot #107396

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4 changes: 0 additions & 4 deletions llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -5559,10 +5559,6 @@ void AArch64InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
if (PNRReg.isValid() && !PNRReg.isVirtual())
MI.addDef(PNRReg, RegState::Implicit);
MI.addMemOperand(MMO);

if (PNRReg.isValid() && PNRReg.isVirtual())
BuildMI(MBB, MBBI, DebugLoc(), get(TargetOpcode::COPY), PNRReg)
.addReg(DestReg);
}

bool llvm::isNZCVTouchedInInstructionRange(const MachineInstr &DefMI,
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37 changes: 36 additions & 1 deletion llvm/test/CodeGen/AArch64/spillfill-sve.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -11,6 +11,7 @@
define aarch64_sve_vector_pcs void @spills_fills_stack_id_ppr2mul2() #0 { entry: unreachable }
define aarch64_sve_vector_pcs void @spills_fills_stack_id_pnr() #1 { entry: unreachable }
define aarch64_sve_vector_pcs void @spills_fills_stack_id_virtreg_pnr() #1 { entry: unreachable }
define aarch64_sve_vector_pcs void @spills_fills_stack_id_virtreg_ppr_to_pnr() #1 { entry: unreachable }
define aarch64_sve_vector_pcs void @spills_fills_stack_id_zpr() #0 { entry: unreachable }
define aarch64_sve_vector_pcs void @spills_fills_stack_id_zpr2() #0 { entry: unreachable }
define aarch64_sve_vector_pcs void @spills_fills_stack_id_zpr2strided() #0 { entry: unreachable }
Expand Down Expand Up @@ -216,7 +217,7 @@ body: |
; EXPAND: STR_PXI killed renamable $pn8, $sp, 7
;
; EXPAND: renamable $pn8 = LDR_PXI $sp, 7
; EXPAND: $p0 = PEXT_PCI_B killed renamable $pn8, 0
; EXPAND-NEXT: $p0 = PEXT_PCI_B killed renamable $pn8, 0


%0:pnr_p8to15 = WHILEGE_CXX_B undef $x0, undef $x0, 0, implicit-def dead $nzcv
Expand All @@ -242,6 +243,40 @@ body: |
RET_ReallyLR
...
---
name: spills_fills_stack_id_virtreg_ppr_to_pnr
tracksRegLiveness: true
registers:
- { id: 0, class: ppr }
- { id: 1, class: pnr_p8to15 }
stack:
body: |
bb.0.entry:
liveins: $p0

%0:ppr = COPY $p0

$pn0 = IMPLICIT_DEF
$pn1 = IMPLICIT_DEF
$pn2 = IMPLICIT_DEF
$pn3 = IMPLICIT_DEF
$pn4 = IMPLICIT_DEF
$pn5 = IMPLICIT_DEF
$pn6 = IMPLICIT_DEF
$pn7 = IMPLICIT_DEF
$pn8 = IMPLICIT_DEF
$pn9 = IMPLICIT_DEF
$pn10 = IMPLICIT_DEF
$pn11 = IMPLICIT_DEF
$pn12 = IMPLICIT_DEF
$pn13 = IMPLICIT_DEF
$pn14 = IMPLICIT_DEF
$pn15 = IMPLICIT_DEF

%1:pnr_p8to15 = COPY %0
$p0 = PEXT_PCI_B %1, 0
RET_ReallyLR
...
---
name: spills_fills_stack_id_zpr
tracksRegLiveness: true
registers:
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