[MIR] Serialize virtual register flags #110228
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✅ With the latest revision this PR passed the C/C++ code formatter. |
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@llvm/pr-subscribers-llvm-globalisel @llvm/pr-subscribers-backend-amdgpu Author: Akshat Oke (Akshat-Oke) Changes[MIR] Serialize virtual register flags This introduces target-specific vreg flag serialization. Flags are represented as Patch is 58.44 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/110228.diff 31 Files Affected:
diff --git a/llvm/include/llvm/CodeGen/MIRParser/MIParser.h b/llvm/include/llvm/CodeGen/MIRParser/MIParser.h
index 7fd9d99ded6995..a1a48f2fb02a81 100644
--- a/llvm/include/llvm/CodeGen/MIRParser/MIParser.h
+++ b/llvm/include/llvm/CodeGen/MIRParser/MIParser.h
@@ -47,6 +47,7 @@ struct VRegInfo {
} D;
Register VReg;
Register PreferredReg;
+ std::vector<::uint8_t> Flags;
};
using Name2RegClassMap = StringMap<const TargetRegisterClass *>;
@@ -150,6 +151,8 @@ struct PerTargetMIParsingState {
/// Return null if the name isn't a register bank.
const RegisterBank *getRegBank(StringRef Name);
+ bool getVRegFlagValue(StringRef FlagName, uint8_t& FlagValue) const;
+
PerTargetMIParsingState(const TargetSubtargetInfo &STI)
: Subtarget(STI) {
initNames2RegClasses();
diff --git a/llvm/include/llvm/CodeGen/MIRYamlMapping.h b/llvm/include/llvm/CodeGen/MIRYamlMapping.h
index ab8dc442e04b7b..e0866cb58802ab 100644
--- a/llvm/include/llvm/CodeGen/MIRYamlMapping.h
+++ b/llvm/include/llvm/CodeGen/MIRYamlMapping.h
@@ -191,6 +191,7 @@ struct VirtualRegisterDefinition {
UnsignedValue ID;
StringValue Class;
StringValue PreferredRegister;
+ std::vector<FlowStringValue> RegisterFlags;
// TODO: Serialize the target specific register hints.
@@ -206,6 +207,8 @@ template <> struct MappingTraits<VirtualRegisterDefinition> {
YamlIO.mapRequired("class", Reg.Class);
YamlIO.mapOptional("preferred-register", Reg.PreferredRegister,
StringValue()); // Don't print out when it's empty.
+ YamlIO.mapOptional("flags", Reg.RegisterFlags,
+ std::vector<FlowStringValue>());
}
static const bool flow = true;
diff --git a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
index 9ea0fba1144b13..6ec38ebb4f886b 100644
--- a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
@@ -1213,6 +1213,15 @@ class TargetRegisterInfo : public MCRegisterInfo {
virtual bool isNonallocatableRegisterCalleeSave(MCRegister Reg) const {
return false;
}
+
+ virtual std::pair<bool, uint8_t> getVRegFlagValue(StringRef Name) const {
+ return {false, 0};
+ }
+
+ virtual SmallVector<std::string>
+ getVRegFlagsOfReg(Register Reg, const MachineFunction &MF) const {
+ return {};
+ }
};
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/CodeGen/MIRParser/MIParser.cpp b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
index a0f0e27478d022..fb3338447798e5 100644
--- a/llvm/lib/CodeGen/MIRParser/MIParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
@@ -127,6 +127,16 @@ bool PerTargetMIParsingState::getRegisterByName(StringRef RegName,
return false;
}
+bool PerTargetMIParsingState::getVRegFlagValue(StringRef FlagName, uint8_t& FlagValue) const {
+ const auto *TRI = Subtarget.getRegisterInfo();
+ assert(TRI && "Expected target register info");
+ auto [HasVReg, FV] = TRI->getVRegFlagValue(FlagName);
+ if(!HasVReg)
+ return true;
+ FlagValue = FV;
+ return false;
+}
+
void PerTargetMIParsingState::initNames2InstrOpCodes() {
if (!Names2InstrOpCodes.empty())
return;
@@ -1776,6 +1786,7 @@ bool MIParser::parseRegisterOperand(MachineOperand &Dest,
MRI.setRegClassOrRegBank(Reg, static_cast<RegisterBank *>(nullptr));
MRI.setType(Reg, Ty);
+ MRI.noteNewVirtualRegister(Reg);
}
}
} else if (consumeIfPresent(MIToken::lparen)) {
diff --git a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
index 997c428ca77dc4..452f6418a65e4b 100644
--- a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
@@ -683,6 +683,15 @@ bool MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
VReg.PreferredRegister.Value, Error))
return error(Error, VReg.PreferredRegister.SourceRange);
}
+
+ for(const auto &FlagStringValue: VReg.RegisterFlags) {
+ uint8_t FlagValue;
+ if(Target->getVRegFlagValue(FlagStringValue.Value, FlagValue))
+ return error(FlagStringValue.SourceRange.Start,
+ Twine("use of undefined register flag '") +
+ FlagStringValue.Value + "'");
+ Info.Flags.push_back(FlagValue);
+ }
}
// Parse the liveins.
diff --git a/llvm/lib/CodeGen/MIRPrinter.cpp b/llvm/lib/CodeGen/MIRPrinter.cpp
index cf6122bce22364..95838c00edb886 100644
--- a/llvm/lib/CodeGen/MIRPrinter.cpp
+++ b/llvm/lib/CodeGen/MIRPrinter.cpp
@@ -113,7 +113,8 @@ class MIRPrinter {
void print(const MachineFunction &MF);
- void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo,
+ void convert(yaml::MachineFunction &YamlMF, const MachineFunction &MF,
+ const MachineRegisterInfo &RegInfo,
const TargetRegisterInfo *TRI);
void convert(ModuleSlotTracker &MST, yaml::MachineFrameInfo &YamlMFI,
const MachineFrameInfo &MFI);
@@ -230,7 +231,7 @@ void MIRPrinter::print(const MachineFunction &MF) {
YamlMF.NoVRegs = MF.getProperties().hasProperty(
MachineFunctionProperties::Property::NoVRegs);
- convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo());
+ convert(YamlMF, MF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo());
MachineModuleSlotTracker MST(MMI, &MF);
MST.incorporateFunction(MF.getFunction());
convert(MST, YamlMF.FrameInfo, MF.getFrameInfo());
@@ -315,10 +316,21 @@ printStackObjectDbgInfo(const MachineFunction::VariableDbgInfo &DebugVar,
}
}
-void MIRPrinter::convert(yaml::MachineFunction &MF,
+static void printRegFlags(Register Reg,
+ std::vector<yaml::FlowStringValue> &RegisterFlags,
+ const MachineFunction &MF,
+ const TargetRegisterInfo *TRI) {
+ SmallVector<std::string> FlagValues = TRI->getVRegFlagsOfReg(Reg, MF);
+ for (auto &Flag : FlagValues) {
+ RegisterFlags.push_back(yaml::FlowStringValue(Flag));
+ }
+}
+
+void MIRPrinter::convert(yaml::MachineFunction &YamlMF,
+ const MachineFunction &MF,
const MachineRegisterInfo &RegInfo,
const TargetRegisterInfo *TRI) {
- MF.TracksRegLiveness = RegInfo.tracksLiveness();
+ YamlMF.TracksRegLiveness = RegInfo.tracksLiveness();
// Print the virtual register definitions.
for (unsigned I = 0, E = RegInfo.getNumVirtRegs(); I < E; ++I) {
@@ -331,7 +343,8 @@ void MIRPrinter::convert(yaml::MachineFunction &MF,
Register PreferredReg = RegInfo.getSimpleHint(Reg);
if (PreferredReg)
printRegMIR(PreferredReg, VReg.PreferredRegister, TRI);
- MF.VirtualRegisters.push_back(VReg);
+ printRegFlags(Reg, VReg.RegisterFlags, MF, TRI);
+ YamlMF.VirtualRegisters.push_back(VReg);
}
// Print the live ins.
@@ -340,7 +353,7 @@ void MIRPrinter::convert(yaml::MachineFunction &MF,
printRegMIR(LI.first, LiveIn.Register, TRI);
if (LI.second)
printRegMIR(LI.second, LiveIn.VirtualRegister, TRI);
- MF.LiveIns.push_back(LiveIn);
+ YamlMF.LiveIns.push_back(LiveIn);
}
// Prints the callee saved registers.
@@ -352,7 +365,7 @@ void MIRPrinter::convert(yaml::MachineFunction &MF,
printRegMIR(*I, Reg, TRI);
CalleeSavedRegisters.push_back(Reg);
}
- MF.CalleeSavedRegisters = CalleeSavedRegisters;
+ YamlMF.CalleeSavedRegisters = CalleeSavedRegisters;
}
}
diff --git a/llvm/test/CodeGen/AMDGPU/limit-coalesce.mir b/llvm/test/CodeGen/AMDGPU/limit-coalesce.mir
index b9105418a588c3..ca774825f4ddef 100644
--- a/llvm/test/CodeGen/AMDGPU/limit-coalesce.mir
+++ b/llvm/test/CodeGen/AMDGPU/limit-coalesce.mir
@@ -2,13 +2,13 @@
# Check that coalescer does not create wider register tuple than in source
-# CHECK: - { id: 2, class: vreg_64, preferred-register: '' }
-# CHECK: - { id: 3, class: vreg_64, preferred-register: '' }
-# CHECK: - { id: 4, class: vreg_64, preferred-register: '' }
-# CHECK: - { id: 5, class: vreg_96, preferred-register: '' }
-# CHECK: - { id: 6, class: vreg_96, preferred-register: '' }
-# CHECK: - { id: 7, class: vreg_128, preferred-register: '' }
-# CHECK: - { id: 8, class: vreg_128, preferred-register: '' }
+# CHECK: - { id: 2, class: vreg_64, preferred-register: '', flags: [ ] }
+# CHECK: - { id: 3, class: vreg_64, preferred-register: '', flags: [ ] }
+# CHECK: - { id: 4, class: vreg_64, preferred-register: '', flags: [ ] }
+# CHECK: - { id: 5, class: vreg_96, preferred-register: '', flags: [ ] }
+# CHECK: - { id: 6, class: vreg_96, preferred-register: '', flags: [ ] }
+# CHECK: - { id: 7, class: vreg_128, preferred-register: '', flags: [ ] }
+# CHECK: - { id: 8, class: vreg_128, preferred-register: '', flags: [ ] }
# No more registers shall be defined
# CHECK-NEXT: liveins:
# CHECK: FLAT_STORE_DWORDX2 $vgpr0_vgpr1, %4,
diff --git a/llvm/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir b/llvm/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir
index 7ed390570adc7c..03f2ec4d6cd3f7 100644
--- a/llvm/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir
+++ b/llvm/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir
@@ -14,8 +14,8 @@ name: test
tracksRegLiveness: true
registers:
- { id: 0, class: gr32 }
- # CHECK: - { id: 1, class: gr32, preferred-register: '%0' }
- # CHECK: - { id: 2, class: gr32, preferred-register: '$edi' }
+ # CHECK: - { id: 1, class: gr32, preferred-register: '%0', flags: [ ] }
+ # CHECK: - { id: 2, class: gr32, preferred-register: '$edi', flags: [ ] }
- { id: 1, class: gr32, preferred-register: '%0' }
- { id: 2, class: gr32, preferred-register: '$edi' }
body: |
diff --git a/llvm/test/CodeGen/MIR/X86/generic-instr-type.mir b/llvm/test/CodeGen/MIR/X86/generic-instr-type.mir
index 710a18ac3aeff4..7514cdab0ab110 100644
--- a/llvm/test/CodeGen/MIR/X86/generic-instr-type.mir
+++ b/llvm/test/CodeGen/MIR/X86/generic-instr-type.mir
@@ -18,11 +18,11 @@
---
name: test_vregs
# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: _, preferred-register: '' }
-# CHECK-NEXT: - { id: 1, class: _, preferred-register: '' }
-# CHECK-NEXT: - { id: 2, class: _, preferred-register: '' }
-# CHECK-NEXT: - { id: 3, class: _, preferred-register: '' }
-# CHECK-NEXT: - { id: 4, class: _, preferred-register: '' }
+# CHECK-NEXT: - { id: 0, class: _, preferred-register: '', flags: [ ] }
+# CHECK-NEXT: - { id: 1, class: _, preferred-register: '', flags: [ ] }
+# CHECK-NEXT: - { id: 2, class: _, preferred-register: '', flags: [ ] }
+# CHECK-NEXT: - { id: 3, class: _, preferred-register: '', flags: [ ] }
+# CHECK-NEXT: - { id: 4, class: _, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
diff --git a/llvm/test/CodeGen/MIR/X86/register-operand-class.mir b/llvm/test/CodeGen/MIR/X86/register-operand-class.mir
index f62d7294eabc10..521722d9f24c54 100644
--- a/llvm/test/CodeGen/MIR/X86/register-operand-class.mir
+++ b/llvm/test/CodeGen/MIR/X86/register-operand-class.mir
@@ -6,11 +6,11 @@
---
# CHECK-LABEL: name: func
# CHECK: registers:
-# CHECK: - { id: 0, class: gr32, preferred-register: '' }
-# CHECK: - { id: 1, class: gr64, preferred-register: '' }
-# CHECK: - { id: 2, class: gr32, preferred-register: '' }
-# CHECK: - { id: 3, class: gr16, preferred-register: '' }
-# CHECK: - { id: 4, class: _, preferred-register: '' }
+# CHECK: - { id: 0, class: gr32, preferred-register: '', flags: [ ] }
+# CHECK: - { id: 1, class: gr64, preferred-register: '', flags: [ ] }
+# CHECK: - { id: 2, class: gr32, preferred-register: '', flags: [ ] }
+# CHECK: - { id: 3, class: gr16, preferred-register: '', flags: [ ] }
+# CHECK: - { id: 4, class: _, preferred-register: '', flags: [ ] }
name: func
body: |
bb.0:
diff --git a/llvm/test/CodeGen/MIR/X86/roundtrip.mir b/llvm/test/CodeGen/MIR/X86/roundtrip.mir
index 46f08ad1a214da..6124113a0dd88f 100644
--- a/llvm/test/CodeGen/MIR/X86/roundtrip.mir
+++ b/llvm/test/CodeGen/MIR/X86/roundtrip.mir
@@ -2,8 +2,8 @@
---
# CHECK-LABEL: name: func0
# CHECK: registers:
-# CHECK: - { id: 0, class: gr32, preferred-register: '' }
-# CHECK: - { id: 1, class: gr32, preferred-register: '' }
+# CHECK: - { id: 0, class: gr32, preferred-register: '', flags: [ ] }
+# CHECK: - { id: 1, class: gr32, preferred-register: '', flags: [ ] }
# CHECK: body: |
# CHECK: bb.0:
# CHECK: %0:gr32 = MOV32r0 implicit-def $eflags
diff --git a/llvm/test/CodeGen/MIR/X86/simple-register-allocation-hints.mir b/llvm/test/CodeGen/MIR/X86/simple-register-allocation-hints.mir
index 84d298dbd40700..aacf66c98cf5d3 100644
--- a/llvm/test/CodeGen/MIR/X86/simple-register-allocation-hints.mir
+++ b/llvm/test/CodeGen/MIR/X86/simple-register-allocation-hints.mir
@@ -15,9 +15,9 @@
name: test
tracksRegLiveness: true
# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' }
-# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '$esi' }
-# CHECK-NEXT: - { id: 2, class: gr32, preferred-register: '$edi' }
+# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '', flags: [ ] }
+# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '$esi', flags: [ ] }
+# CHECK-NEXT: - { id: 2, class: gr32, preferred-register: '$edi', flags: [ ] }
registers:
- { id: 0, class: gr32 }
- { id: 1, class: gr32, preferred-register: '$esi' }
diff --git a/llvm/test/CodeGen/MIR/X86/virtual-registers.mir b/llvm/test/CodeGen/MIR/X86/virtual-registers.mir
index e317746e08a18e..819f65638b67de 100644
--- a/llvm/test/CodeGen/MIR/X86/virtual-registers.mir
+++ b/llvm/test/CodeGen/MIR/X86/virtual-registers.mir
@@ -33,9 +33,9 @@
name: bar
tracksRegLiveness: true
# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' }
-# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '' }
-# CHECK-NEXT: - { id: 2, class: gr32, preferred-register: '' }
+# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '', flags: [ ] }
+# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '', flags: [ ] }
+# CHECK-NEXT: - { id: 2, class: gr32, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: gr32 }
- { id: 1, class: gr32 }
@@ -67,9 +67,9 @@ name: foo
tracksRegLiveness: true
# CHECK: name: foo
# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' }
-# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '' }
-# CHECK-NEXT: - { id: 2, class: gr32, preferred-register: '' }
+# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '', flags: [ ] }
+# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '', flags: [ ] }
+# CHECK-NEXT: - { id: 2, class: gr32, preferred-register: '', flags: [ ] }
registers:
- { id: 2, class: gr32 }
- { id: 0, class: gr32 }
diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v128.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v128.mir
index 3b8455684f33d2..881ceac1d1f7f2 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v128.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v128.mir
@@ -26,9 +26,9 @@ alignment: 16
legalized: false
regBankSelected: false
# ALL: registers:
-# ALL-NEXT: - { id: 0, class: _, preferred-register: '' }
-# ALL-NEXT: - { id: 1, class: _, preferred-register: '' }
-# ALL-NEXT: - { id: 2, class: _, preferred-register: '' }
+# ALL-NEXT: - { id: 0, class: _, preferred-register: '', flags: [ ] }
+# ALL-NEXT: - { id: 1, class: _, preferred-register: '', flags: [ ] }
+# ALL-NEXT: - { id: 2, class: _, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@@ -56,9 +56,9 @@ alignment: 16
legalized: false
regBankSelected: false
# ALL: registers:
-# ALL-NEXT: - { id: 0, class: _, preferred-register: '' }
-# ALL-NEXT: - { id: 1, class: _, preferred-register: '' }
-# ALL-NEXT: - { id: 2, class: _, preferred-register: '' }
+# ALL-NEXT: - { id: 0, class: _, preferred-register: '', flags: [ ] }
+# ALL-NEXT: - { id: 1, class: _, preferred-register: '', flags: [ ] }
+# ALL-NEXT: - { id: 2, class: _, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@@ -86,9 +86,9 @@ alignment: 16
legalized: false
regBankSelected: false
# ALL: registers:
-# ALL-NEXT: - { id: 0, class: _, preferred-register: '' }
-# ALL-NEXT: - { id: 1, class: _, preferred-register: '' }
-# ALL-NEXT: - { id: 2, class: _, preferred-register: '' }
+# ALL-NEXT: - { id: 0, class: _, preferred-register: '', flags: [ ] }
+# ALL-NEXT: - { id: 1, class: _, preferred-register: '', flags: [ ] }
+# ALL-NEXT: - { id: 2, class: _, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v256.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v256.mir
index 4965b069715a11..c2800bef9713de 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v256.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v256.mir
@@ -26,9 +26,9 @@ alignment: 16
legalized: false
regBankSelected: false
# ALL: registers:
-# ALL-NEXT: - { id: 0, class: _, preferred-register: '' }
-# ALL-NEXT: - { id: 1, class: _, preferred-register: '' }
-# ALL-NEXT: - { id: 2, class: _, preferred-register: '' }
+# ALL-NEXT: - { id: 0, class: _, preferred-register: '', flags: [ ] }
+# ALL-NEXT: - { id: 1, class: _, preferred-register: '', flags: [ ] }
+# ALL-NEXT: - { id: 2, class: _, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@@ -56,9 +56,9 @@ alignment: 16
legalized: false
regBankSelected: false
# ALL: registers:
-# ALL-NEXT: - { id: 0, class: _, preferred-register: '' }
-# ALL-NEXT: - { id: 1, class: _, preferred-register: '' }
-# ALL-NEXT: - { id: 2, class: _, preferred-register: '' }
+# ALL-NEXT: - { id: 0, class: _, preferred-register: '', flags: [ ] }
+# ALL-NEXT: - { id: 1, class: _, preferred-register: '', flags: [ ] }
+# ALL-NEXT: - { id: 2, class: _, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@@ -86,9 +86,9 @@ alignment: 16
legalized: false
regBankSelected: false
# ALL: registers:
-# ALL-NEXT: - { id: 0, class: _, preferred-register: '' }
-# ALL-NEXT: - { id: 1, class: _, preferred-register: '' }
-# ALL-NEXT: - { id: 2, class: _, preferred-register: '' }
+# ALL-NEXT: - { id: 0, class: _, preferred-register: '', flags: [ ] }
+# ALL-NEXT: - { id: 1, class: _, preferred-register: '', flags: [ ] }
+# ALL-NEXT: - { id: 2, class: _, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v512.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v512.mir
index 77a94581b66fde..e45818af22a356 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v512.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v512.mir
@@ -28,9 +28,9 @@ alignment: 16
legalized: false
regBankSelected: false
# ALL: registers:
-# ALL-NEXT: - { id: 0, class: _, preferred-register: '' }
-# ALL-NEXT: - { id: 1, class: _, preferred-register: '' }
-# ALL-NEXT: - { id: 2, class: _, preferred-register: '' }
+# ALL-NEXT: - { id: 0, class: _, preferred-register: '', flags: [ ] }
+# ALL-NEXT: - { id: 1, class: _, preferred-register: '', flags: [ ] }
+# ALL-NEXT: - { id: 2, class: _, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@@ -58,9 +58,9 @@ alignment: 16
legalized: false
regBankSelected: false
# ALL: registers:
-# ALL-NEXT: - { id: 0, class: _, preferred-register: '' }
-# ALL-NEXT: - { id: 1, class: _, preferred-register: '' }
-# ALL-NEXT: - { id: 2, class: _, preferred-register: '' }
+# ALL-NEXT: - { id: 0, class: _, preferred-register: '', flags: [ ] }
+# ALL-NEXT: - { id: 1, class: _, preferred-...
[truncated]
|
jayfoad
reviewed
Sep 27, 2024
I believe that would require changing how YamlO prints optional fields, unless there is another way to do it here I don't know of. |
|
Missing new test for this serialized field. |
topperc
reviewed
Sep 28, 2024
topperc
reviewed
Sep 28, 2024
|
|
||
| for(const auto &FlagStringValue: VReg.RegisterFlags) { | ||
| uint8_t FlagValue; | ||
| if(Target->getVRegFlagValue(FlagStringValue.Value, FlagValue)) |
There was a problem hiding this comment.
yup, somehow forgot to clang format
Ignore this comment. I just noticed the other review (#110229) where you're adding the target-specific changes. |
topperc
reviewed
Sep 28, 2024
For the other fields, I thought this changed based on the -simplify-mir flag. (Also, -simplify-mir should really be the default) |
arsenm
reviewed
Sep 29, 2024
| @@ -47,6 +47,7 @@ struct VRegInfo { | |||
| } D; | |||
| Register VReg; | |||
| Register PreferredReg; | |||
| std::vector<::uint8_t> Flags; | |||
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There's a struct named uint8_t defined in this class.
I believe the author meant enum : uint8_t instead.
| uint8_t FlagValue; | ||
| if(Target->getVRegFlagValue(FlagStringValue.Value, FlagValue)) | ||
| return error(FlagStringValue.SourceRange.Start, | ||
| Twine("use of undefined register flag '") + |
That does the job, thanks. |
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LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/190/builds/7569 Here is the relevant piece of the build log for the reference |
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LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/185/builds/6774 Here is the relevant piece of the build log for the reference |
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[MIR] Serialize virtual register flags llvm#110228 introduces register flags which appear empty in .mir dumps. Future tests should use -simplify-mir.
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[MIR] Serialize virtual register flags #110228 introduces register flags which appear empty in .mir dumps. Future tests should use `-simplify-mir`.
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A fix-it patch for dbfca24 #110228. No need for a container. This allows 8 flags for a register. The virtual register flags vector had a memory leak because the vector's memory is not freed. The `BumpPtrAllocator` handles the deallocation and missed calling the `std::vector<uint8_t> Flags` destructor.
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[MIR] Serialize virtual register flags This introduces target-specific vreg flag serialization. Flags are represented as `uint8_t` and the `TargetRegisterInfo` override provides methods `getVRegFlagValue` to deserialize and `getVRegFlagsOfReg` to serialize.
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[MIR] Serialize virtual register flags llvm#110228 introduces register flags which appear empty in .mir dumps. Future tests should use `-simplify-mir`.
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[MIR] Serialize virtual register flags
This introduces target-specific vreg flag serialization. Flags are represented as
uint8_tand theTargetRegisterInfooverride provides methodsgetVRegFlagValueto deserialize andgetVRegFlagsOfRegto serialize.