Reland [AMDGPU] Serialize WWM_REG vreg flag (#110229) #112492
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@llvm/pr-subscribers-backend-amdgpu Author: Akshat Oke (optimisan) ChangesA reland but not an exact copy as Full diff: https://github.com/llvm/llvm-project/pull/112492.diff 4 Files Affected:
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index e4cc522194f2a9..4d94faf5facf81 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -1718,6 +1718,13 @@ bool GCNTargetMachine::parseMachineFunctionInfo(
MFI->reserveWWMRegister(ParsedReg);
}
+ for (const auto &[_, Info] : PFS.VRegInfosNamed) {
+ MFI->setFlag(Info->VReg, Info->Flags);
+ }
+ for (const auto &[_, Info] : PFS.VRegInfos) {
+ MFI->setFlag(Info->VReg, Info->Flags);
+ }
+
auto parseAndCheckArgument = [&](const std::optional<yaml::SIArgument> &A,
const TargetRegisterClass &RC,
ArgDescriptor &Arg, unsigned UserSGPRs,
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index de9cbe403ab618..20d48aa57adbdf 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -3851,3 +3851,13 @@ SIRegisterInfo::getSubRegAlignmentNumBits(const TargetRegisterClass *RC,
}
return 0;
}
+
+SmallVector<StringLiteral>
+SIRegisterInfo::getVRegFlagsOfReg(Register Reg,
+ const MachineFunction &MF) const {
+ SmallVector<StringLiteral> RegFlags;
+ const SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>();
+ if (FuncInfo->checkFlag(Reg, AMDGPU::VirtRegFlag::WWM_REG))
+ RegFlags.push_back("WWM_REG");
+ return RegFlags;
+}
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
index 99fa632c0300be..fe0b66f75bbaa2 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
@@ -457,6 +457,14 @@ class SIRegisterInfo final : public AMDGPUGenRegisterInfo {
// No check if the subreg is supported by the current RC is made.
unsigned getSubRegAlignmentNumBits(const TargetRegisterClass *RC,
unsigned SubReg) const;
+
+ std::optional<uint8_t> getVRegFlagValue(StringRef Name) const override {
+ return Name == "WWM_REG" ? AMDGPU::VirtRegFlag::WWM_REG
+ : std::optional<uint8_t>{};
+ }
+
+ SmallVector<StringLiteral>
+ getVRegFlagsOfReg(Register Reg, const MachineFunction &MF) const override;
};
namespace AMDGPU {
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir
index ebbb89b7816c58..51795a4fea515e 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir
@@ -578,3 +578,18 @@ body: |
SI_RETURN
...
+---
+name: vregs
+# FULL: registers:
+# FULL-NEXT: - { id: 0, class: vgpr_32, preferred-register: '$vgpr1', flags: [ WWM_REG ] }
+# FULL-NEXT: - { id: 1, class: sgpr_64, preferred-register: '$sgpr0_sgpr1', flags: [ ] }
+# FULL-NEXT: - { id: 2, class: sgpr_64, preferred-register: '', flags: [ ] }
+registers:
+ - { id: 0, class: vgpr_32, preferred-register: $vgpr1, flags: [ WWM_REG ]}
+ - { id: 1, class: sgpr_64, preferred-register: $sgpr0_sgpr1 }
+ - { id: 2, class: sgpr_64, flags: [ ] }
+body: |
+ bb.0:
+ %2:sgpr_64 = COPY %1
+ %1:sgpr_64 = COPY %0
+...
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arsenm
approved these changes
Oct 16, 2024
cdevadas
approved these changes
Oct 18, 2024
optimisan
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LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/88/builds/3681 Here is the relevant piece of the build log for the reference |
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Working on it |
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Could not reproduce the failure |
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A reland but not an exact copy as
VRegInfo.Flagsfrom the parser is now an int8 instead of a vector; so only need to copy over the value.