[SystemZ] Introduce GNU and HLASM differences to asmwriter and update tests #113369
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@llvm/pr-subscribers-backend-systemz Author: None (tltao) ChangesNow that the GNU and HLASM The main difference are:
Patch is 53.38 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/113369.diff 15 Files Affected:
diff --git a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZHLASMInstPrinter.cpp b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZHLASMInstPrinter.cpp
index ed7ff83a3c6df0..e3eb1e608cf334 100644
--- a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZHLASMInstPrinter.cpp
+++ b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZHLASMInstPrinter.cpp
@@ -30,6 +30,12 @@ void SystemZHLASMInstPrinter::printInst(const MCInst *MI, uint64_t Address,
StringRef Annot,
const MCSubtargetInfo &STI,
raw_ostream &O) {
- printInstruction(MI, Address, O);
+ std::string Str;
+ raw_string_ostream RSO(Str);
+ printInstruction(MI, Address, RSO);
+ // Eat the first tab character and replace it with a space since it is
+ // hardcoded in AsmWriterEmitter::EmitPrintInstruction
+ // TODO: introduce a line prefix member to AsmWriter to avoid this problem
+ O << " " << Str.substr(1, Str.length());
printAnnotation(O, Annot);
}
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
index 50f636a8d9686c..6e136b10aed428 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
+++ b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
@@ -18,7 +18,8 @@ class InstSystemZ<int size, dag outs, dag ins, string asmstr,
dag InOperandList = ins;
let Size = size;
let Pattern = pattern;
- let AsmString = asmstr;
+ // Convert tabs to spaces, and remove space after comma for HLASM syntax
+ let AsmString = !subst("\t", "{\t| }", !subst(", ", "{, |,}", asmstr));
let hasSideEffects = 0;
let mayLoad = 0;
diff --git a/llvm/test/CodeGen/SystemZ/call-zos-01.ll b/llvm/test/CodeGen/SystemZ/call-zos-01.ll
index fc7a85caa37eb0..7ad1e4c4679ebc 100644
--- a/llvm/test/CodeGen/SystemZ/call-zos-01.ll
+++ b/llvm/test/CodeGen/SystemZ/call-zos-01.ll
@@ -3,14 +3,14 @@
; RUN: llc < %s -mtriple=s390x-ibm-zos -mcpu=z10 | FileCheck %s
; CHECK-LABEL: call_char:
-; CHECK: lghi 1, 8
+; CHECK: lghi 1,8
define i8 @call_char(){
%retval = call i8 (i8) @pass_char(i8 8)
ret i8 %retval
}
; CHECK-LABEL: call_short:
-; CHECK: lghi 1, 16
+; CHECK: lghi 1,16
define i16 @call_short() {
entry:
%retval = call i16 (i16) @pass_short(i16 16)
@@ -18,8 +18,8 @@ entry:
}
; CHECK-LABEL: call_int:
-; CHECK: lghi 1, 32
-; CHECK: lghi 2, 33
+; CHECK: lghi 1,32
+; CHECK: lghi 2,33
define i32 @call_int() {
entry:
%retval = call i32 (i32, i32) @pass_int(i32 32, i32 33)
@@ -27,9 +27,9 @@ entry:
}
; CHECK-LABEL: call_long:
-; CHECK: lghi 1, 64
-; CHECK: lghi 2, 65
-; CHECK: lghi 3, 66
+; CHECK: lghi 1,64
+; CHECK: lghi 2,65
+; CHECK: lghi 3,66
define i64 @call_long() {
entry:
%retval = call i64 (i64, i64, i64) @pass_long(i64 64, i64 65, i64 66)
@@ -37,7 +37,7 @@ entry:
}
; CHECK-LABEL: call_ptr:
-; CHECK: lgr 1, 2
+; CHECK: lgr 1,2
define i32 @call_ptr(ptr %p1, ptr %p2) {
entry:
%retval = call i32 (ptr) @pass_ptr(ptr %p2)
@@ -45,9 +45,9 @@ entry:
}
; CHECK-LABEL: call_integrals:
-; CHECK: lghi 1, 64
-; CHECK: lghi 2, 32
-; CHECK: lghi 3, 16
+; CHECK: lghi 1,64
+; CHECK: lghi 2,32
+; CHECK: lghi 3,16
define i64 @call_integrals() {
entry:
%retval = call i64 (i64, i32, i16, i64) @pass_integrals0(i64 64, i32 32, i16 16, i64 128)
@@ -55,29 +55,29 @@ entry:
}
; CHECK-LABEL: pass_char:
-; CHECK: lgr 3, 1
+; CHECK: lgr 3,1
define signext i8 @pass_char(i8 signext %arg) {
entry:
ret i8 %arg
}
; CHECK-LABEL: pass_short:
-; CHECK: lgr 3, 1
+; CHECK: lgr 3,1
define signext i16 @pass_short(i16 signext %arg) {
entry:
ret i16 %arg
}
; CHECK-LABEL: pass_int:
-; CHECK: lgr 3, 2
+; CHECK: lgr 3,2
define signext i32 @pass_int(i32 signext %arg0, i32 signext %arg1) {
entry:
ret i32 %arg1
}
; CHECK-LABEL: pass_long:
-; CHECK: agr 1, 2
-; CHECK: agr 3, 1
+; CHECK: agr 1,2
+; CHECK: agr 3,1
define signext i64 @pass_long(i64 signext %arg0, i64 signext %arg1, i64 signext %arg2) {
entry:
%N = add i64 %arg0, %arg1
@@ -86,8 +86,8 @@ entry:
}
; CHECK-LABEL: pass_integrals0:
-; CHECK: ag 2, 2200(4)
-; CHECK-NEXT: lgr 3, 2
+; CHECK: ag 2,2200(4)
+; CHECK-NEXT: lgr 3,2
define signext i64 @pass_integrals0(i64 signext %arg0, i32 signext %arg1, i16 signext %arg2, i64 signext %arg3) {
entry:
%N = sext i32 %arg1 to i64
@@ -96,7 +96,7 @@ entry:
}
; CHECK-LABEL: call_float:
-; CHECK: le 0, 0({{[0-9]}})
+; CHECK: le 0,0({{[0-9]}})
define float @call_float() {
entry:
%ret = call float (float) @pass_float(float 0x400921FB60000000)
@@ -104,8 +104,8 @@ entry:
}
; CHECK-LABEL: call_double:
-; CHECK: larl [[GENREG:[0-9]+]], L#{{CPI[0-9]+_[0-9]+}}
-; CHECK-NEXT: ld 0, 0([[GENREG]])
+; CHECK: larl [[GENREG:[0-9]+]],L#{{CPI[0-9]+_[0-9]+}}
+; CHECK-NEXT: ld 0,0([[GENREG]])
define double @call_double() {
entry:
%ret = call double (double) @pass_double(double 3.141000e+00)
@@ -113,9 +113,9 @@ entry:
}
; CHECK-LABEL: call_longdouble:
-; CHECK: larl [[GENREG:[0-9]+]], L#{{CPI[0-9]+_[0-9]+}}
-; CHECK-NEXT: ld 0, 0([[GENREG]])
-; CHECK-NEXT: ld 2, 8([[GENREG]])
+; CHECK: larl [[GENREG:[0-9]+]],L#{{CPI[0-9]+_[0-9]+}}
+; CHECK-NEXT: ld 0,0([[GENREG]])
+; CHECK-NEXT: ld 2,8([[GENREG]])
define fp128 @call_longdouble() {
entry:
%ret = call fp128 (fp128) @pass_longdouble(fp128 0xLE0FC1518450562CD4000921FB5444261)
@@ -123,12 +123,12 @@ entry:
}
; CHECK-LABEL: call_floats0
-; CHECK: larl [[GENREG:[0-9]+]], L#{{CPI[0-9]+_[0-9]+}}
-; CHECK-NEXT: ld 1, 0([[GENREG]])
-; CHECK-NEXT: ld 3, 8([[GENREG]])
-; CHECK: lxr 5, 0
-; CHECK: lxr 0, 1
-; CHECK: lxr 4, 5
+; CHECK: larl [[GENREG:[0-9]+]],L#{{CPI[0-9]+_[0-9]+}}
+; CHECK-NEXT: ld 1,0([[GENREG]])
+; CHECK-NEXT: ld 3,8([[GENREG]])
+; CHECK: lxr 5,0
+; CHECK: lxr 0,1
+; CHECK: lxr 4,5
define i64 @call_floats0(fp128 %arg0, double %arg1) {
entry:
%ret = call i64 (fp128, fp128, double) @pass_floats0(fp128 0xLE0FC1518450562CD4000921FB5444261, fp128 %arg0, double %arg1)
@@ -136,9 +136,9 @@ entry:
}
; CHECK-LABEL: call_floats1
-; CHECK: lxr 1, 0
-; CHECK: ldr 0, 4
-; CHECK: lxr 4, 1
+; CHECK: lxr 1,0
+; CHECK: ldr 0,4
+; CHECK: lxr 4,1
define i64 @call_floats1(fp128 %arg0, double %arg1) {
entry:
%ret = call i64 (double, fp128) @pass_floats1(double %arg1, fp128 %arg0)
@@ -146,8 +146,8 @@ entry:
}
; CHECK-LABEL: pass_float:
-; CHECK: larl 1, L#{{CPI[0-9]+_[0-9]+}}
-; CHECK: aeb 0, 0(1)
+; CHECK: larl 1,L#{{CPI[0-9]+_[0-9]+}}
+; CHECK: aeb 0,0(1)
define float @pass_float(float %arg) {
entry:
%X = fadd float %arg, 0x400821FB60000000
@@ -155,8 +155,8 @@ entry:
}
; CHECK-LABEL: pass_double:
-; CHECK: larl 1, L#{{CPI[0-9]+_[0-9]+}}
-; CHECK: adb 0, 0(1)
+; CHECK: larl 1,L#{{CPI[0-9]+_[0-9]+}}
+; CHECK: adb 0,0(1)
define double @pass_double(double %arg) {
entry:
%X = fadd double %arg, 1.414213e+00
@@ -164,9 +164,9 @@ entry:
}
; CHECK-LABEL: pass_longdouble
-; CHECK: larl 1, L#{{CPI[0-9]+_[0-9]+}}
-; CHECK: lxdb 1, 0(1)
-; CHECK: axbr 0, 1
+; CHECK: larl 1,L#{{CPI[0-9]+_[0-9]+}}
+; CHECK: lxdb 1,0(1)
+; CHECK: axbr 0,1
define fp128 @pass_longdouble(fp128 %arg) {
entry:
%X = fadd fp128 %arg, 0xL10000000000000004000921FB53C8D4F
@@ -174,10 +174,10 @@ entry:
}
; CHECK-LABEL: pass_floats0
-; CHECK: larl 1, L#{{CPI[0-9]+_[0-9]+}}
-; CHECK: axbr 0, 4
-; CHECK: axbr 1, 0
-; CHECK: cxbr 1, 5
+; CHECK: larl 1,L#{{CPI[0-9]+_[0-9]+}}
+; CHECK: axbr 0,4
+; CHECK: axbr 1,0
+; CHECK: cxbr 1,5
define i64 @pass_floats0(fp128 %arg0, fp128 %arg1, double %arg2) {
%X = fadd fp128 %arg0, %arg1
%arg2_ext = fpext double %arg2 to fp128
diff --git a/llvm/test/CodeGen/SystemZ/call-zos-02.ll b/llvm/test/CodeGen/SystemZ/call-zos-02.ll
index 29e3e275bedc49..444972fa8765ed 100644
--- a/llvm/test/CodeGen/SystemZ/call-zos-02.ll
+++ b/llvm/test/CodeGen/SystemZ/call-zos-02.ll
@@ -9,9 +9,9 @@ entry:
define hidden signext i32 @caller2() {
entry:
; CHECK-LABEL: caller2:
-; CHECK: brasl 7, caller@PLT * encoding: [0xc0,0x75,A,A,A,A]
+; CHECK: brasl 7,caller@PLT * encoding: [0xc0,0x75,A,A,A,A]
; CHECK-NEXT: * fixup A - offset: 2, value: caller@PLT+2, kind: FK_390_PC32DBL
-; CHECK-NEXT: bcr 0, 3 * encoding: [0x07,0x03]
+; CHECK-NEXT: bcr 0,3 * encoding: [0x07,0x03]
%call = call signext i32 @caller()
ret i32 %call
}
diff --git a/llvm/test/CodeGen/SystemZ/call-zos-i128.ll b/llvm/test/CodeGen/SystemZ/call-zos-i128.ll
index 775483374a32f3..98c3d84bc8bf90 100644
--- a/llvm/test/CodeGen/SystemZ/call-zos-i128.ll
+++ b/llvm/test/CodeGen/SystemZ/call-zos-i128.ll
@@ -3,15 +3,15 @@
; RUN: llc < %s -mtriple=s390x-ibm-zos -mcpu=z13 | FileCheck %s
; CHECK-LABEL: call_i128:
-; CHECK-DAG: larl 1, L#CPI0_0
-; CHECK-DAG: vl 0, 0(1), 3
-; CHECK-DAG: vst 0, 2256(4), 3
-; CHECK-DAG: larl 1, L#CPI0_1
-; CHECK-DAG: vl 0, 0(1), 3
-; CHECK-DAG: vst 0, 2272(4), 3
-; CHECK-DAG: la 1, 2288(4)
-; CHECK-DAG: la 2, 2272(4)
-; CHECK-DAG: la 3, 2256(4)
+; CHECK-DAG: larl 1,L#CPI0_0
+; CHECK-DAG: vl 0,0(1),3
+; CHECK-DAG: vst 0,2256(4),3
+; CHECK-DAG: larl 1,L#CPI0_1
+; CHECK-DAG: vl 0,0(1),3
+; CHECK-DAG: vst 0,2272(4),3
+; CHECK-DAG: la 1,2288(4)
+; CHECK-DAG: la 2,2272(4)
+; CHECK-DAG: la 3,2256(4)
define i128 @call_i128() {
entry:
@@ -20,10 +20,10 @@ entry:
}
; CHECK-LABEL: pass_i128:
-; CHECK: vl 0, 0(3), 3
-; CHECK: vl 1, 0(2), 3
-; CHECK: vaq 0, 1, 0
-; CHECK: vst 0, 0(1), 3
+; CHECK: vl 0,0(3),3
+; CHECK: vl 1,0(2),3
+; CHECK: vaq 0,1,0
+; CHECK: vst 0,0(1),3
define i128 @pass_i128(i128 %arg0, i128 %arg1) {
entry:
%N = add i128 %arg0, %arg1
diff --git a/llvm/test/CodeGen/SystemZ/call-zos-vararg.ll b/llvm/test/CodeGen/SystemZ/call-zos-vararg.ll
index 81aedc1a1d7f2d..72f4d79610e0e4 100644
--- a/llvm/test/CodeGen/SystemZ/call-zos-vararg.ll
+++ b/llvm/test/CodeGen/SystemZ/call-zos-vararg.ll
@@ -2,18 +2,18 @@
; RUN: llc < %s -mtriple=s390x-ibm-zos -mcpu=z10 | FileCheck %s
; RUN: llc < %s -mtriple=s390x-ibm-zos -mcpu=z14 | FileCheck %s -check-prefix=ARCH12
; CHECK-LABEL: call_vararg_double0:
-; CHECK: stmg 6, 7, 1872(4)
-; CHECK-NEXT: aghi 4, -192
-; CHECK-NEXT: lg 6, 8(5)
-; CHECK-NEXT: lg 5, 0(5)
-; CHECK-NEXT: llihf 3, 1074118262
-; CHECK-NEXT: oilf 3, 3367254360
-; CHECK-NEXT: lghi 1, 1
-; CHECK-NEXT: lghi 2, 2
-; CHECK-NEXT: basr 7, 6
-; CHECK-NEXT: bcr 0, 0
-; CHECK-NEXT: lg 7, 2072(4)
-; CHECK-NEXT: aghi 4, 192
+; CHECK: stmg 6,7,1872(4)
+; CHECK-NEXT: aghi 4,-192
+; CHECK-NEXT: lg 6,8(5)
+; CHECK-NEXT: lg 5,0(5)
+; CHECK-NEXT: llihf 3,1074118262
+; CHECK-NEXT: oilf 3,3367254360
+; CHECK-NEXT: lghi 1,1
+; CHECK-NEXT: lghi 2,2
+; CHECK-NEXT: basr 7,6
+; CHECK-NEXT: bcr 0,0
+; CHECK-NEXT: lg 7,2072(4)
+; CHECK-NEXT: aghi 4,192
; CHECK-NEXT: b 2(7)
define i64 @call_vararg_double0() {
entry:
@@ -22,21 +22,21 @@ entry:
}
; CHECK-LABEL: call_vararg_double1:
-; CHECK: stmg 6, 7, 1872(4)
-; CHECK-NEXT: aghi 4, -192
-; CHECK-NEXT: llihf 0, 1074118262
-; CHECK-NEXT: oilf 0, 3367254360
-; CHECK-NEXT: lg 6, 8(5)
-; CHECK-NEXT: lg 5, 0(5)
-; CHECK-NEXT: llihf 3, 1074340036
-; CHECK-NEXT: oilf 3, 2611340116
-; CHECK-NEXT: lghi 1, 1
-; CHECK-NEXT: lghi 2, 2
-; CHECK-NEXT: stg 0, 2200(4)
-; CHECK-NEXT: basr 7, 6
-; CHECK-NEXT: bcr 0, 0
-; CHECK-NEXT: lg 7, 2072(4)
-; CHECK-NEXT: aghi 4, 192
+; CHECK: stmg 6,7,1872(4)
+; CHECK-NEXT: aghi 4,-192
+; CHECK-NEXT: llihf 0,1074118262
+; CHECK-NEXT: oilf 0,3367254360
+; CHECK-NEXT: lg 6,8(5)
+; CHECK-NEXT: lg 5,0(5)
+; CHECK-NEXT: llihf 3,1074340036
+; CHECK-NEXT: oilf 3,2611340116
+; CHECK-NEXT: lghi 1,1
+; CHECK-NEXT: lghi 2,2
+; CHECK-NEXT: stg 0,2200(4)
+; CHECK-NEXT: basr 7,6
+; CHECK-NEXT: bcr 0,0
+; CHECK-NEXT: lg 7,2072(4)
+; CHECK-NEXT: aghi 4,192
; CHECK-NEXT: b 2(7)
define i64 @call_vararg_double1() {
entry:
@@ -45,17 +45,17 @@ entry:
}
; CHECK-LABEL: call_vararg_double2:
-; CHECK: stmg 6, 7, 1872(4)
-; CHECK-NEXT: aghi 4, -192
-; CHECK-NEXT: lg 6, 24(5)
-; CHECK-NEXT: lg 5, 16(5)
-; CHECK-NEXT: llihf 2, 1074118262
-; CHECK-NEXT: oilf 2, 3367254360
-; CHECK-NEXT: lghi 1, 8200
-; CHECK-NEXT: basr 7, 6
-; CHECK-NEXT: bcr 0, 0
-; CHECK-NEXT: lg 7, 2072(4)
-; CHECK-NEXT: aghi 4, 192
+; CHECK: stmg 6,7,1872(4)
+; CHECK-NEXT: aghi 4,-192
+; CHECK-NEXT: lg 6,24(5)
+; CHECK-NEXT: lg 5,16(5)
+; CHECK-NEXT: llihf 2,1074118262
+; CHECK-NEXT: oilf 2,3367254360
+; CHECK-NEXT: lghi 1,8200
+; CHECK-NEXT: basr 7,6
+; CHECK-NEXT: bcr 0,0
+; CHECK-NEXT: lg 7,2072(4)
+; CHECK-NEXT: aghi 4,192
; CHECK-NEXT: b 2(7)
define i64 @call_vararg_double2() {
entry:
@@ -64,23 +64,23 @@ entry:
}
; CHECK-LABEL: call_vararg_double3:
-; CHECK: stmg 6, 7, 1872(4)
-; CHECK-NEXT: aghi 4, -192
-; CHECK-NEXT: llihf 0, 1072703839
-; CHECK-NEXT: oilf 0, 2861204133
-; CHECK-NEXT: lg 6, 40(5)
-; CHECK-NEXT: lg 5, 32(5)
-; CHECK-NEXT: llihf 1, 1074118262
-; CHECK-NEXT: oilf 1, 3367254360
-; CHECK-NEXT: llihf 2, 1074340036
-; CHECK-NEXT: oilf 2, 2611340116
-; CHECK-NEXT: llihf 3, 1073127358
-; CHECK-NEXT: oilf 3, 1992864825
-; CHECK-NEXT: stg 0, 2200(4)
-; CHECK-NEXT: basr 7, 6
-; CHECK-NEXT: bcr 0, 0
-; CHECK-NEXT: lg 7, 2072(4)
-; CHECK-NEXT: aghi 4, 192
+; CHECK: stmg 6,7,1872(4)
+; CHECK-NEXT: aghi 4,-192
+; CHECK-NEXT: llihf 0,1072703839
+; CHECK-NEXT: oilf 0,2861204133
+; CHECK-NEXT: lg 6,40(5)
+; CHECK-NEXT: lg 5,32(5)
+; CHECK-NEXT: llihf 1,1074118262
+; CHECK-NEXT: oilf 1,3367254360
+; CHECK-NEXT: llihf 2,1074340036
+; CHECK-NEXT: oilf 2,2611340116
+; CHECK-NEXT: llihf 3,1073127358
+; CHECK-NEXT: oilf 3,1992864825
+; CHECK-NEXT: stg 0,2200(4)
+; CHECK-NEXT: basr 7,6
+; CHECK-NEXT: bcr 0,0
+; CHECK-NEXT: lg 7,2072(4)
+; CHECK-NEXT: aghi 4,192
; CHECK-NEXT: b 2(7)
define i64 @call_vararg_double3() {
entry:
@@ -90,17 +90,17 @@ entry:
;; TODO: The extra COPY after LGDR is unnecessary (machine-scheduler introduces the overlap).
; CHECK-LABEL: call_vararg_both0:
-; CHECK: stmg 6, 7, 1872(4)
-; CHECK-NEXT: aghi 4, -192
-; CHECK-NEXT: lg 6, 40(5)
-; CHECK-NEXT: lg 5, 32(5)
-; CHECK-NEXT: lgdr 0, 0
-; CHECK-NEXT: lgr 2, 1
-; CHECK-NEXT: lgr 1, 0
-; CHECK-NEXT: basr 7, 6
-; CHECK-NEXT: bcr 0, 0
-; CHECK-NEXT: lg 7, 2072(4)
-; CHECK-NEXT: aghi 4, 192
+; CHECK: stmg 6,7,1872(4)
+; CHECK-NEXT: aghi 4,-192
+; CHECK-NEXT: lg 6,40(5)
+; CHECK-NEXT: lg 5,32(5)
+; CHECK-NEXT: lgdr 0,0
+; CHECK-NEXT: lgr 2,1
+; CHECK-NEXT: lgr 1,0
+; CHECK-NEXT: basr 7,6
+; CHECK-NEXT: bcr 0,0
+; CHECK-NEXT: lg 7,2072(4)
+; CHECK-NEXT: aghi 4,192
; CHECK-NEXT: b 2(7)
define i64 @call_vararg_both0(i64 %arg0, double %arg1) {
%retval = call i64(...) @pass_vararg3(double %arg1, i64 %arg0)
@@ -108,22 +108,22 @@ define i64 @call_vararg_both0(i64 %arg0, double %arg1) {
}
; CHECK-LABEL: call_vararg_long_double0:
-; CHECK: stmg 6, 7, 1872(4)
-; CHECK-NEXT: aghi 4, -192
-; CHECK-NEXT: larl 1, L#CPI5_0
-; CHECK-NEXT: ld 0, 0(1)
-; CHECK-NEXT: ld 2, 8(1)
-; CHECK-NEXT: lg 6, 8(5)
-; CHECK-NEXT: lg 5, 0(5)
-; CHECK-NEXT: lgdr 3, 0
-; CHECK-NEXT: lghi 1, 1
-; CHECK-NEXT: lghi 2, 2
-; CHECK-NEXT: std 0, 2192(4)
-; CHECK-NEXT: std 2, 2200(4)
-; CHECK-NEXT: basr 7, 6
-; CHECK-NEXT: bcr 0, 0
-; CHECK-NEXT: lg 7, 2072(4)
-; CHECK-NEXT: aghi 4, 192
+; CHECK: stmg 6,7,1872(4)
+; CHECK-NEXT: aghi 4,-192
+; CHECK-NEXT: larl 1,L#CPI5_0
+; CHECK-NEXT: ld 0,0(1)
+; CHECK-NEXT: ld 2,8(1)
+; CHECK-NEXT: lg 6,8(5)
+; CHECK-NEXT: lg 5,0(5)
+; CHECK-NEXT: lgdr 3,0
+; CHECK-NEXT: lghi 1,1
+; CHECK-NEXT: lghi 2,2
+; CHECK-NEXT: std 0,2192(4)
+; CHECK-NEXT: std 2,2200(4)
+; CHECK-NEXT: basr 7,6
+; CHECK-NEXT: bcr 0,0
+; CHECK-NEXT: lg 7,2072(4)
+; CHECK-NEXT: aghi 4,192
; CHECK-NEXT: b 2(7)
define i64 @call_vararg_long_double0() {
entry:
@@ -132,19 +132,19 @@ entry:
}
; CHECK-LABEL: call_vararg_long_double1:
-; CHECK: stmg 6, 7, 1872(4)
-; CHECK-NEXT: aghi 4, -192
-; CHECK-NEXT: lg 6, 8(5)
-; CHECK-NEXT: lg 5, 0(5)
-; CHECK-NEXT: lgdr 3, 0
-; CHECK-NEXT: lghi 1, 1
-; CHECK-NEXT: lghi 2, 2
-; CHECK-NEXT: std 0, 2192(4)
-; CHECK-NEXT: std 2, 2200(4)
-; CHECK-NEXT: basr 7, 6
-; CHECK-NEXT: bcr 0, 0
-; CHECK-NEXT: lg 7, 2072(4)
-; CHECK-NEXT: aghi 4, 192
+; CHECK: stmg 6,7,1872(4)
+; CHECK-NEXT: aghi 4,-192
+; CHECK-NEXT: lg 6,8(5)
+; CHECK-NEXT: lg 5,0(5)
+; CHECK-NEXT: lgdr 3,0
+; CHECK-NEXT: lghi 1,1
+; CHECK-NEXT: lghi 2,2
+; CHECK-NEXT: std 0,2192(4)
+; CHECK-NEXT: std 2,2200(4)
+; CHECK-NEXT: basr 7,6
+; CHECK-NEXT: bcr 0,0
+; CHECK-NEXT: lg 7,2072(4)
+; CHECK-NEXT: aghi 4,192
; CHECK-NEXT: b 2(7)
define i64 @call_vararg_long_double1(fp128 %arg0) {
entry:
@@ -154,21 +154,21 @@ entry:
; CHECK-LABEL: call_vararg_long_double2
; CHECK-LABEL: call_vararg_long_double2:
-; CHECK: stmg 6, 7, 1872(4)
-; CHECK-NEXT: aghi 4, -192
-; CHECK-NEXT: std 4, 2208(4)
-; CHECK-NEXT: std 6, 2216(4)
-; CHECK-NEXT: lg 6, 8(5)
-; CHECK-NEXT: lg 5, 0(5)
-; CHECK-NEXT: lgdr 3, 0
-; CHECK-NEXT: lghi 1, 1
-; CHECK-NEXT: lghi 2, 2
-; CHECK-NEXT: std 0, 2192(4)
-; CHECK-NEXT: std 2, 2200(4)
-; CHECK-NEXT: basr 7, 6
-; CHECK-NEXT: bcr 0, 0
-; CHECK-NEXT: lg 7, 2072(4)
-; CHECK-NEXT: aghi 4, 192
+; CHECK: stmg 6,7,1872(4)
+; CHECK-NEXT: aghi 4,-192
+; CHECK-NEXT: std 4,2208(4)
+; CHECK-NEXT: std 6,2216(4)
+; CHECK-NEXT: lg 6,8(5)
+; CHECK-NEXT: lg 5,0(5)
+; CHECK-NEXT: lgdr 3,0
+; CHECK-NEXT: lghi 1,1
+; CHECK-NEXT: lghi 2,2
+; CHECK-NEXT: std 0,2192(4)
+; CHECK-NEXT: std 2,2200(4)
+; CHECK-NEXT: basr 7,6
+; CHECK-NEXT: bcr 0,0
+; CHECK-NEXT: lg 7,2072(4)
+; CHECK-NEXT: aghi 4,192
; CHECK-NEXT: b 2(7)
define i64 @call_vararg_long_double2(fp128 %arg0, fp128 %arg1) {
entry:
@@ -177,16 +177,16 @@ entry:
}
; CHECK-LABEL: call_vararg_long_double3:
-; CHECK: stmg 6, 7, 1872(4)
-; CHECK-NEXT: aghi 4, -192
-; CHECK-NEXT: lg 6, 40(5)
-; CHECK-NEXT: lg 5, 32(5)
-; CHECK-NEXT: lgdr 3, 2
-; CHECK-NEXT: lgdr 2, 0
-; CHECK-NEXT: basr 7, 6
-; CHECK-NEXT: bcr 0, 0
-; CHECK-NEXT: lg 7, 2072(4)
-; CHECK-NEXT: aghi 4, 192
+; CHECK: stmg 6,7,1872(4)
+; CHECK-NEXT: aghi 4,-192
+; CHECK-NEXT: lg 6,40(5)
+; CHECK-NEXT: lg 5,32(5)
+; CHECK-NEXT: lgdr 3,2
+; CHECK-NEXT: lgdr 2,0
+; CHECK-NEXT: basr 7,6
+; CHECK-NEXT: bcr 0,0
+; CHECK-NEXT: lg 7,2072(4)
+; CHECK-NEXT: aghi 4,192
; CHECK-NEXT: b 2(7)
define i64 @call_vararg_long_double3(fp128 %arg0) {
entry:
@@ -195,77 +195,77 @@ entry:
}
; ARCH12-LABEL: call_vec_vararg_test0
-; ARCH12: vlgvg 3, 24, 1
-; ARCH12: vlgvg 2, 24, 0
-; ARCH12: lghi 1, 1
+; ARCH12: vlgvg 3,24,1
+; ARCH12: vlgvg 2,24,0
+; ARCH12: lghi 1,1
define void @call_vec_vararg_test0(<2 x double> %v) {
%retval = call i64(i64, ...) @pass_vararg2(i64 1, <2 x double> %v)
ret void
}
; ARCH12-LABEL: call_vec_vararg_test1
-; ARCH12: larl 1, L#CPI10_0
-; ARCH12: vl 0, 0(1), 3
-; ARCH12: vlgvg 3, 24, 0
-; ARCH12: vrepg 2, 0, 1
-; ARCH12: vst 25, 2208(4), 3
-; ARCH12: vst 24, 2192(4), 3
+; ARCH12: larl 1,L#CPI10_0
+; ARCH12: vl 0,0(1),3
+; ARCH12: vlgvg 3,24,0
+; ARCH12: vrepg 2,0,1
+; ARCH12: vst 25,2208(4),3
+; ARCH12: vst 24,2192(4),3
define void @call_vec_vararg_test1(<4 x i32> %v, <2 x i64> %w) {
%retval = call i64(fp128, ...) @pass_vararg1(fp128 0xLE0FC1518450562CD4000921FB5444261, <4 x i32> %v, <2 x i64> %w)
ret void
}
; ARCH12-LABEL: call_vec_char_vararg_straddle
-; ARCH12: vlgvg 3, 24, 0
-; ARCH12: lghi 1, 1
-; ARCH12: lghi 2, 2
-; ARCH12: vst 24, 2192(4), 3
+; ARCH12: vlgvg 3,24,0
+; ARCH12: lghi 1,1
+; ARCH12: lghi 2,2
+; ARCH12: vst 24,2192(4),3
define void @call_vec_char_vararg_straddle(<16 x i8> %v) {
%retval = call i64(i64, i64, ...) @pass_vararg0(i64 1, i64 2, <16 x i8> %v)
ret void
}
; ARCH12-LABEL: call_vec_short_vararg_stra...
[truncated]
|
uweigand
approved these changes
Oct 23, 2024
|
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/30/builds/8794 Here is the relevant piece of the build log for the reference |
tltao
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Oct 24, 2024
Fix buildbot failures seen on: https://lab.llvm.org/buildbot/#/builders/42/builds/1597 caused by: #113369 Co-authored-by: Tony Tao <[email protected]>
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NoumanAmir657
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Nov 4, 2024
… tests (llvm#113369) Now that the GNU and HLASM `InstPrinter` paths are separated in llvm#112975, differentiate between them in `SystemZInstrFormats.td`. The main difference are: - Tabs converted to space - Remove space after comma for instruction operands --------- Co-authored-by: Tony Tao <[email protected]>
NoumanAmir657
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that referenced
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Nov 4, 2024
Fix buildbot failures seen on: https://lab.llvm.org/buildbot/#/builders/42/builds/1597 caused by: llvm#113369 Co-authored-by: Tony Tao <[email protected]>
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Now that the GNU and HLASM
InstPrinterpaths are separated in #112975, differentiate between them inSystemZInstrFormats.td.The main difference are: