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Merged
merged 2 commits into from
Dec 12, 2024
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[M68k] Add remaining addressing modes for Atomic operations #115523

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4ef9a85
[M68k] Add tests for atomics under large code model, with and without…
knickish Nov 7, 2024
2827514
[M68k] Add missing addressing modes for atomic ops
knickish Nov 4, 2024
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8 changes: 7 additions & 1 deletion llvm/lib/Target/M68k/Disassembler/M68kDisassembler.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -19,8 +19,8 @@

#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCDisassembler/MCDisassembler.h"
#include "llvm/MC/MCDecoderOps.h"
#include "llvm/MC/MCDisassembler/MCDisassembler.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/Endian.h"
Expand Down Expand Up @@ -83,6 +83,12 @@ static DecodeStatus DecodeXR32RegisterClass(MCInst &Inst, uint64_t RegNo,
return DecodeRegisterClass(Inst, RegNo, Address, Decoder);
}

static DecodeStatus DecodeXR32RegisterClass(MCInst &Inst, APInt RegNo,
uint64_t Address,
const void *Decoder) {
return DecodeRegisterClass(Inst, RegNo.getZExtValue(), Address, Decoder);
}

static DecodeStatus DecodeXR16RegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
const void *Decoder) {
Expand Down
18 changes: 17 additions & 1 deletion llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp
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Expand Up @@ -708,6 +708,20 @@ bool M68kDAGToDAGISel::SelectARIPD(SDNode *Parent, SDValue N, SDValue &Base) {
return false;
}

[[maybe_unused]] static bool allowARIDWithDisp(SDNode *Parent) {
if (!Parent)
return false;
switch (Parent->getOpcode()) {
case ISD::LOAD:
case ISD::STORE:
case ISD::ATOMIC_LOAD:
case ISD::ATOMIC_STORE:
return true;
default:
return false;
}
}

bool M68kDAGToDAGISel::SelectARID(SDNode *Parent, SDValue N, SDValue &Disp,
SDValue &Base) {
LLVM_DEBUG(dbgs() << "Selecting AddrType::ARID: ");
Expand Down Expand Up @@ -740,7 +754,8 @@ bool M68kDAGToDAGISel::SelectARID(SDNode *Parent, SDValue N, SDValue &Disp,
Base = AM.BaseReg;

if (getSymbolicDisplacement(AM, SDLoc(N), Disp)) {
assert(!AM.Disp && "Should not be any displacement");
assert((!AM.Disp || allowARIDWithDisp(Parent)) &&
"Should not be any displacement");
LLVM_DEBUG(dbgs() << "SUCCESS, matched Symbol\n");
return true;
}
Expand Down Expand Up @@ -780,6 +795,7 @@ static bool AllowARIIWithZeroDisp(SDNode *Parent) {
case ISD::STORE:
case ISD::ATOMIC_LOAD:
case ISD::ATOMIC_STORE:
case ISD::ATOMIC_CMP_SWAP:
return true;
default:
return false;
Expand Down
89 changes: 81 additions & 8 deletions llvm/lib/Target/M68k/M68kInstrAtomics.td
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Expand Up @@ -13,17 +13,38 @@ foreach size = [8, 16, 32] in {
def : Pat<(!cast<SDPatternOperator>("atomic_load_"#size) MxCP_ARII:$ptr),
(!cast<MxInst>("MOV"#size#"df") !cast<MxMemOp>("MxARII"#size):$ptr)>;

def : Pat<(!cast<SDPatternOperator>("atomic_load_"#size) MxCP_ARID:$ptr),
(!cast<MxInst>("MOV"#size#"dp") !cast<MxMemOp>("MxARID"#size):$ptr)>;

def : Pat<(!cast<SDPatternOperator>("atomic_load_"#size) MxCP_PCD:$ptr),
(!cast<MxInst>("MOV"#size#"dq") !cast<MxMemOp>("MxPCD"#size):$ptr)>;

def : Pat<(!cast<SDPatternOperator>("atomic_load_"#size) MxCP_PCI:$ptr),
(!cast<MxInst>("MOV"#size#"dk") !cast<MxMemOp>("MxPCI"#size):$ptr)>;

def : Pat<(!cast<SDPatternOperator>("atomic_store_"#size) !cast<MxRegOp>("MxDRD"#size):$val, MxCP_ARI:$ptr),
(!cast<MxInst>("MOV"#size#"jd") !cast<MxMemOp>("MxARI"#size):$ptr,
!cast<MxRegOp>("MxDRD"#size):$val)>;

def : Pat<(!cast<SDPatternOperator>("atomic_store_"#size) !cast<MxRegOp>("MxDRD"#size):$val, MxCP_ARII:$ptr),
(!cast<MxInst>("MOV"#size#"fd") !cast<MxMemOp>("MxARII"#size):$ptr,
!cast<MxRegOp>("MxDRD"#size):$val)>;

def : Pat<(!cast<SDPatternOperator>("atomic_store_"#size) !cast<MxRegOp>("MxDRD"#size):$val, MxCP_ARID:$ptr),
(!cast<MxInst>("MOV"#size#"pd") !cast<MxMemOp>("MxARID"#size):$ptr,
!cast<MxRegOp>("MxDRD"#size):$val)>;

def : Pat<(!cast<SDPatternOperator>("atomic_store_"#size) !cast<MxRegOp>("MxDRD"#size):$val, MxCP_PCD:$ptr),
(!cast<MxInst>("MOV"#size#"qd") !cast<MxMemOp>("MxPCD"#size):$ptr,
!cast<MxRegOp>("MxDRD"#size):$val)>;

def : Pat<(!cast<SDPatternOperator>("atomic_store_"#size) !cast<MxRegOp>("MxDRD"#size):$val, MxCP_PCI:$ptr),
(!cast<MxInst>("MOV"#size#"kd") !cast<MxMemOp>("MxPCI"#size):$ptr,
!cast<MxRegOp>("MxDRD"#size):$val)>;
}

let Predicates = [AtLeastM68020] in {
class MxCASOp<bits<2> size_encoding, MxType type>
class MxCASARIOp<bits<2> size_encoding, MxType type>
: MxInst<(outs type.ROp:$out),
(ins type.ROp:$dc, type.ROp:$du, !cast<MxMemOp>("MxARI"#type.Size):$mem),
"cas."#type.Prefix#" $dc, $du, $mem"> {
Expand All @@ -36,17 +57,69 @@ class MxCASOp<bits<2> size_encoding, MxType type>
let mayStore = 1;
}

def CAS8 : MxCASOp<0x1, MxType8d>;
def CAS16 : MxCASOp<0x2, MxType16d>;
def CAS32 : MxCASOp<0x3, MxType32d>;
def CASARI8 : MxCASARIOp<0x1, MxType8d>;
def CASARI16 : MxCASARIOp<0x2, MxType16d>;
def CASARI32 : MxCASARIOp<0x3, MxType32d>;

class MxCASARIDOp<bits<2> size_encoding, MxType type>
: MxInst<(outs type.ROp:$out),
(ins type.ROp:$dc, type.ROp:$du, !cast<MxMemOp>("MxARID"#type.Size):$mem),
"cas."#type.Prefix#" $dc, $du, $mem"> {
let Inst = (ascend
(descend 0b00001, size_encoding, 0b011, MxEncAddrMode_p<"mem">.EA),
(descend 0b0000000, (operand "$du", 3), 0b000, (operand "$dc", 3))
);
let Constraints = "$out = $dc";
let mayLoad = 1;
let mayStore = 1;
}

def CASARID8 : MxCASARIDOp<0x1, MxType8d>;
def CASARID16 : MxCASARIDOp<0x2, MxType16d>;
def CASARID32 : MxCASARIDOp<0x3, MxType32d>;

class MxCASARIIOp<bits<2> size_encoding, MxType type>
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Do we have MC tests for these new instructions (I assume you already have their codegen tests)? If not, could you add them?

Ditto for other CAS variants below.

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Added a new test at llvm/test/MC/M68k/Atomics/cas.s which shows all of them except ARD, which I couldn't get to parse for some reason. I was getting an illegal operand error when I tried to add cas.w %d4, %d5, %a3 as a test case. Am I expecting something to work incorrectly here, or is it likely an issue with the AsmParser?

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On further investigation, looks like PC-relative and ARD addressing modes are not legal for CAS, will have to lower these to some different instruction sequences

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Removed the offending modes for now, as it looks like the code changes will be in different files. All of the addressing modes added by the patch are now tested in the new MC test

: MxInst<(outs type.ROp:$out),
(ins type.ROp:$dc, type.ROp:$du, !cast<MxMemOp>("MxARII"#type.Size):$mem),
"cas."#type.Prefix#" $dc, $du, $mem"> {
let Inst = (ascend
(descend 0b00001, size_encoding, 0b011, MxEncAddrMode_f<"mem">.EA),
(descend 0b0000000, (operand "$du", 3), 0b000, (operand "$dc", 3))
);
let Constraints = "$out = $dc";
let mayLoad = 1;
let mayStore = 1;
}

def CASARII8 : MxCASARIIOp<0x1, MxType8d>;
def CASARII16 : MxCASARIIOp<0x2, MxType16d>;
def CASARII32 : MxCASARIIOp<0x3, MxType32d>;

class MxCASALOp<bits<2> size_encoding, MxType type>
: MxInst<(outs type.ROp:$out),
(ins type.ROp:$dc, type.ROp:$du, !cast<MxMemOp>("MxAL"#type.Size):$mem),
"cas."#type.Prefix#" $dc, $du, $mem"> {
let Inst = (ascend
(descend 0b00001, size_encoding, 0b011, MxEncAddrMode_abs<"mem">.EA),
(descend 0b0000000, (operand "$du", 3), 0b000, (operand "$dc", 3))
);
let Constraints = "$out = $dc";
let mayLoad = 1;
let mayStore = 1;
}

def CASAL8 : MxCASALOp<0x1, MxType8d>;
def CASAL16 : MxCASALOp<0x2, MxType16d>;
def CASAL32 : MxCASALOp<0x3, MxType32d>;

foreach mode = ["ARI", "ARII", "ARID", "AL"] in {
foreach size = [8, 16, 32] in {
def : Pat<(!cast<SDPatternOperator>("atomic_cmp_swap_i"#size) MxCP_ARI:$ptr,
def : Pat<(!cast<SDPatternOperator>("atomic_cmp_swap_i"#size) !cast<ComplexPattern>("MxCP_"#mode):$ptr,
!cast<MxRegOp>("MxDRD"#size):$cmp,
!cast<MxRegOp>("MxDRD"#size):$new),
(!cast<MxInst>("CAS"#size) !cast<MxRegOp>("MxDRD"#size):$cmp,
(!cast<MxInst>("CAS"#mode#size) !cast<MxRegOp>("MxDRD"#size):$cmp,
!cast<MxRegOp>("MxDRD"#size):$new,
!cast<MxMemOp>("MxARI"#size):$ptr)>;
}
!cast<MxMemOp>("Mx"#mode#size):$ptr)>;
} // size
} // addr mode
} // let Predicates = [AtLeastM68020]
48 changes: 48 additions & 0 deletions llvm/test/CodeGen/M68k/Atomics/load-store.ll
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Expand Up @@ -604,3 +604,51 @@ define void @atomic_store_i64_seq_cst(ptr %a, i64 %val) nounwind {
store atomic i64 %val, ptr %a seq_cst, align 8
ret void
}

define void @store_arid(ptr nonnull align 4 %a) {
; NO-ATOMIC-LABEL: store_arid:
; NO-ATOMIC: .cfi_startproc
; NO-ATOMIC-NEXT: ; %bb.0: ; %start
; NO-ATOMIC-NEXT: moveq #1, %d0
; NO-ATOMIC-NEXT: move.l (4,%sp), %a0
; NO-ATOMIC-NEXT: move.l %d0, (32,%a0)
; NO-ATOMIC-NEXT: rts
;
; ATOMIC-LABEL: store_arid:
; ATOMIC: .cfi_startproc
; ATOMIC-NEXT: ; %bb.0: ; %start
; ATOMIC-NEXT: moveq #1, %d0
; ATOMIC-NEXT: move.l (4,%sp), %a0
; ATOMIC-NEXT: move.l %d0, (32,%a0)
; ATOMIC-NEXT: rts
start:
%1 = getelementptr inbounds i32, ptr %a, i32 8
store atomic i32 1, ptr %1 seq_cst, align 4
br label %exit

exit: ; preds = %start
ret void
}

define i32 @load_arid(ptr nonnull align 4 %a) {
; NO-ATOMIC-LABEL: load_arid:
; NO-ATOMIC: .cfi_startproc
; NO-ATOMIC-NEXT: ; %bb.0: ; %start
; NO-ATOMIC-NEXT: move.l (4,%sp), %a0
; NO-ATOMIC-NEXT: move.l (32,%a0), %d0
; NO-ATOMIC-NEXT: rts
;
; ATOMIC-LABEL: load_arid:
; ATOMIC: .cfi_startproc
; ATOMIC-NEXT: ; %bb.0: ; %start
; ATOMIC-NEXT: move.l (4,%sp), %a0
; ATOMIC-NEXT: move.l (32,%a0), %d0
; ATOMIC-NEXT: rts
start:
%1 = getelementptr inbounds i32, ptr %a, i32 8
%2 = load atomic i32, ptr %1 seq_cst, align 4
br label %exit

exit: ; preds = %start
ret i32 %2
}
141 changes: 141 additions & 0 deletions llvm/test/CodeGen/M68k/Atomics/rmw.ll
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Expand Up @@ -588,3 +588,144 @@ entry:
%old = atomicrmw xchg ptr %ptr, i32 %val monotonic
ret i32 %old
}

define i8 @atomicrmw_sub_i8_arid(ptr align 2 %self) {
; NO-ATOMIC-LABEL: atomicrmw_sub_i8_arid:
; NO-ATOMIC: .cfi_startproc
; NO-ATOMIC-NEXT: ; %bb.0: ; %start
; NO-ATOMIC-NEXT: suba.l #12, %sp
; NO-ATOMIC-NEXT: .cfi_def_cfa_offset -16
; NO-ATOMIC-NEXT: move.l (16,%sp), %a0
; NO-ATOMIC-NEXT: move.l (%a0), %d0
; NO-ATOMIC-NEXT: add.l #4, %d0
; NO-ATOMIC-NEXT: move.l %d0, (%sp)
; NO-ATOMIC-NEXT: move.l #1, (4,%sp)
; NO-ATOMIC-NEXT: jsr __sync_fetch_and_sub_1
; NO-ATOMIC-NEXT: adda.l #12, %sp
; NO-ATOMIC-NEXT: rts
;
; ATOMIC-LABEL: atomicrmw_sub_i8_arid:
; ATOMIC: .cfi_startproc
; ATOMIC-NEXT: ; %bb.0: ; %start
; ATOMIC-NEXT: suba.l #4, %sp
; ATOMIC-NEXT: .cfi_def_cfa_offset -8
; ATOMIC-NEXT: movem.l %d2, (0,%sp) ; 8-byte Folded Spill
; ATOMIC-NEXT: move.l (8,%sp), %a0
; ATOMIC-NEXT: move.l (%a0), %a0
; ATOMIC-NEXT: move.b (4,%a0), %d1
; ATOMIC-NEXT: move.b %d1, %d0
; ATOMIC-NEXT: .LBB12_1: ; %atomicrmw.start
; ATOMIC-NEXT: ; =>This Inner Loop Header: Depth=1
; ATOMIC-NEXT: move.b %d1, %d2
; ATOMIC-NEXT: add.b #-1, %d2
; ATOMIC-NEXT: cas.b %d0, %d2, (4,%a0)
; ATOMIC-NEXT: move.b %d0, %d2
; ATOMIC-NEXT: sub.b %d1, %d2
; ATOMIC-NEXT: seq %d1
; ATOMIC-NEXT: sub.b #1, %d1
; ATOMIC-NEXT: move.b %d0, %d1
; ATOMIC-NEXT: bne .LBB12_1
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-NEXT: movem.l (0,%sp), %d2 ; 8-byte Folded Reload
; ATOMIC-NEXT: adda.l #4, %sp
; ATOMIC-NEXT: rts
start:
%self1 = load ptr, ptr %self, align 2
%_18.i.i = getelementptr inbounds i8, ptr %self1, i32 4
%6 = atomicrmw sub ptr %_18.i.i, i8 1 release, align 4
ret i8 %6
}

define i16 @atomicrmw_sub_i16_arid(ptr align 2 %self) {
; NO-ATOMIC-LABEL: atomicrmw_sub_i16_arid:
; NO-ATOMIC: .cfi_startproc
; NO-ATOMIC-NEXT: ; %bb.0: ; %start
; NO-ATOMIC-NEXT: suba.l #12, %sp
; NO-ATOMIC-NEXT: .cfi_def_cfa_offset -16
; NO-ATOMIC-NEXT: move.l (16,%sp), %a0
; NO-ATOMIC-NEXT: move.l (%a0), %d0
; NO-ATOMIC-NEXT: add.l #4, %d0
; NO-ATOMIC-NEXT: move.l %d0, (%sp)
; NO-ATOMIC-NEXT: move.l #1, (4,%sp)
; NO-ATOMIC-NEXT: jsr __sync_fetch_and_sub_2
; NO-ATOMIC-NEXT: adda.l #12, %sp
; NO-ATOMIC-NEXT: rts
;
; ATOMIC-LABEL: atomicrmw_sub_i16_arid:
; ATOMIC: .cfi_startproc
; ATOMIC-NEXT: ; %bb.0: ; %start
; ATOMIC-NEXT: suba.l #4, %sp
; ATOMIC-NEXT: .cfi_def_cfa_offset -8
; ATOMIC-NEXT: movem.l %d2, (0,%sp) ; 8-byte Folded Spill
; ATOMIC-NEXT: move.l (8,%sp), %a0
; ATOMIC-NEXT: move.l (%a0), %a0
; ATOMIC-NEXT: move.w (4,%a0), %d1
; ATOMIC-NEXT: move.w %d1, %d0
; ATOMIC-NEXT: .LBB13_1: ; %atomicrmw.start
; ATOMIC-NEXT: ; =>This Inner Loop Header: Depth=1
; ATOMIC-NEXT: move.w %d1, %d2
; ATOMIC-NEXT: add.w #-1, %d2
; ATOMIC-NEXT: cas.w %d0, %d2, (4,%a0)
; ATOMIC-NEXT: move.w %d0, %d2
; ATOMIC-NEXT: sub.w %d1, %d2
; ATOMIC-NEXT: seq %d1
; ATOMIC-NEXT: sub.b #1, %d1
; ATOMIC-NEXT: move.w %d0, %d1
; ATOMIC-NEXT: bne .LBB13_1
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-NEXT: movem.l (0,%sp), %d2 ; 8-byte Folded Reload
; ATOMIC-NEXT: adda.l #4, %sp
; ATOMIC-NEXT: rts
start:
%self1 = load ptr, ptr %self, align 2
%_18.i.i = getelementptr inbounds i8, ptr %self1, i32 4
%6 = atomicrmw sub ptr %_18.i.i, i16 1 release, align 4
ret i16 %6
}

define i32 @atomicrmw_sub_i32_arid(ptr align 2 %self) {
; NO-ATOMIC-LABEL: atomicrmw_sub_i32_arid:
; NO-ATOMIC: .cfi_startproc
; NO-ATOMIC-NEXT: ; %bb.0: ; %start
; NO-ATOMIC-NEXT: suba.l #12, %sp
; NO-ATOMIC-NEXT: .cfi_def_cfa_offset -16
; NO-ATOMIC-NEXT: move.l (16,%sp), %a0
; NO-ATOMIC-NEXT: move.l (%a0), %d0
; NO-ATOMIC-NEXT: add.l #4, %d0
; NO-ATOMIC-NEXT: move.l %d0, (%sp)
; NO-ATOMIC-NEXT: move.l #1, (4,%sp)
; NO-ATOMIC-NEXT: jsr __sync_fetch_and_sub_4
; NO-ATOMIC-NEXT: adda.l #12, %sp
; NO-ATOMIC-NEXT: rts
;
; ATOMIC-LABEL: atomicrmw_sub_i32_arid:
; ATOMIC: .cfi_startproc
; ATOMIC-NEXT: ; %bb.0: ; %start
; ATOMIC-NEXT: suba.l #4, %sp
; ATOMIC-NEXT: .cfi_def_cfa_offset -8
; ATOMIC-NEXT: movem.l %d2, (0,%sp) ; 8-byte Folded Spill
; ATOMIC-NEXT: move.l (8,%sp), %a0
; ATOMIC-NEXT: move.l (%a0), %a0
; ATOMIC-NEXT: move.l (4,%a0), %d1
; ATOMIC-NEXT: move.l %d1, %d0
; ATOMIC-NEXT: .LBB14_1: ; %atomicrmw.start
; ATOMIC-NEXT: ; =>This Inner Loop Header: Depth=1
; ATOMIC-NEXT: move.l %d1, %d2
; ATOMIC-NEXT: add.l #-1, %d2
; ATOMIC-NEXT: cas.l %d0, %d2, (4,%a0)
; ATOMIC-NEXT: move.l %d0, %d2
; ATOMIC-NEXT: sub.l %d1, %d2
; ATOMIC-NEXT: seq %d1
; ATOMIC-NEXT: sub.b #1, %d1
; ATOMIC-NEXT: move.l %d0, %d1
; ATOMIC-NEXT: bne .LBB14_1
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-NEXT: movem.l (0,%sp), %d2 ; 8-byte Folded Reload
; ATOMIC-NEXT: adda.l #4, %sp
; ATOMIC-NEXT: rts
start:
%self1 = load ptr, ptr %self, align 2
%_18.i.i = getelementptr inbounds i8, ptr %self1, i32 4
%6 = atomicrmw sub ptr %_18.i.i, i32 1 release, align 4
ret i32 %6
}
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