Skip to content

[SPIRV] Addition of @llvm.lround.* and @llvm.llround.* intrinsic #129240

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
wants to merge 2 commits into
base: main
Choose a base branch
from
Open

[SPIRV] Addition of @llvm.lround.* and @llvm.llround.* intrinsic #129240

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
c5dadbc
--Added legalizer for @llvm.lround.* and @llvm.llround.* inrinsic
aadeshps-mcw Feb 28, 2025
24ad081
Merge branch 'main' into aadesh
michalpaszkowski Apr 29, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
63 changes: 62 additions & 1 deletion llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -275,6 +275,12 @@ class SPIRVInstructionSelector : public InstructionSelector {
GL::GLSLExtInst GLInst) const;
bool selectExtInst(Register ResVReg, const SPIRVType *ResType,
MachineInstr &I, const ExtInstList &ExtInsts) const;
bool selectExtInstForLRound(Register ResVReg, const SPIRVType *ResType,
MachineInstr &I, CL::OpenCLExtInst CLInst,
GL::GLSLExtInst GLInst) const;
bool selectExtInstForLRound(Register ResVReg, const SPIRVType *ResType,
MachineInstr &I,
const ExtInstList &ExtInsts) const;

bool selectLog10(Register ResVReg, const SPIRVType *ResType,
MachineInstr &I) const;
Expand Down Expand Up @@ -678,7 +684,26 @@ bool SPIRVInstructionSelector::spvSelect(Register ResVReg,
return selectSUCmp(ResVReg, ResType, I, true);
case TargetOpcode::G_UCMP:
return selectSUCmp(ResVReg, ResType, I, false);

case TargetOpcode::G_LROUND:
case TargetOpcode::G_LLROUND: {
Register regForLround =
MRI->createVirtualRegister(MRI->getRegClass(ResVReg), "lround");
MRI->setRegClass(regForLround, &SPIRV::iIDRegClass);
GR.assignSPIRVTypeToVReg(GR.getSPIRVTypeForVReg(I.getOperand(1).getReg()),
regForLround, *(I.getParent()->getParent()));
bool isRounded = selectExtInstForLRound(
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Can it ever be false? if yes, we should prevent fallthrough

regForLround, GR.getSPIRVTypeForVReg(regForLround), I, CL::round,
GL::Round);
if (isRounded) {
MachineBasicBlock &BB = *I.getParent();
MachineFunction &MF = *BB.getParent();
auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpConvertFToS))
.addDef(ResVReg)
.addUse(GR.getSPIRVTypeID(ResType))
.addUse(regForLround);
return MIB.constrainAllUses(TII, TRI, RBI);
}
}
case TargetOpcode::G_STRICT_FMA:
case TargetOpcode::G_FMA:
return selectExtInst(ResVReg, ResType, I, CL::fma, GL::Fma);
Expand Down Expand Up @@ -1017,6 +1042,42 @@ bool SPIRVInstructionSelector::selectExtInst(Register ResVReg,
}
return false;
}
bool SPIRVInstructionSelector::selectExtInstForLRound(
Register ResVReg, const SPIRVType *ResType, MachineInstr &I,
CL::OpenCLExtInst CLInst, GL::GLSLExtInst GLInst) const {
ExtInstList ExtInsts = {{SPIRV::InstructionSet::OpenCL_std, CLInst},
{SPIRV::InstructionSet::GLSL_std_450, GLInst}};
return selectExtInstForLRound(ResVReg, ResType, I, ExtInsts);
}

bool SPIRVInstructionSelector::selectExtInstForLRound(
Register ResVReg, const SPIRVType *ResType, MachineInstr &I,
const ExtInstList &Insts) const {

Comment on lines +1055 to +1056
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

lets remove an empty line

Suggested change
const ExtInstList &Insts) const {
const ExtInstList &Insts) const {

for (const auto &Ex : Insts) {
SPIRV::InstructionSet::InstructionSet Set = Ex.first;
uint32_t Opcode = Ex.second;
if (STI.canUseExtInstSet(Set)) {
MachineBasicBlock &BB = *I.getParent();
auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpExtInst))
.addDef(ResVReg)
.addUse(GR.getSPIRVTypeID(ResType))
.addImm(static_cast<uint32_t>(Set))
.addImm(Opcode);
const unsigned NumOps = I.getNumOperands();
unsigned Index = 1;
if (Index < NumOps &&
I.getOperand(Index).getType() ==
MachineOperand::MachineOperandType::MO_IntrinsicID)
Index = 2;
for (; Index < NumOps; ++Index)
MIB.add(I.getOperand(Index));
MIB.constrainAllUses(TII, TRI, RBI);
return true;
}
}
return false;
}

bool SPIRVInstructionSelector::selectOpWithSrcs(Register ResVReg,
const SPIRVType *ResType,
Expand Down
4 changes: 4 additions & 0 deletions llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -270,6 +270,10 @@ SPIRVLegalizerInfo::SPIRVLegalizerInfo(const SPIRVSubtarget &ST) {
{G_UADDO, G_SADDO, G_USUBO, G_SSUBO, G_UMULO, G_SMULO})
.alwaysLegal();

getActionDefinitionsBuilder({G_LROUND, G_LLROUND})
.legalForCartesianProduct(allFloatScalarsAndVectors,
allIntScalarsAndVectors);

// FP conversions.
getActionDefinitionsBuilder({G_FPTRUNC, G_FPEXT})
.legalForCartesianProduct(allFloatScalarsAndVectors);
Expand Down
106 changes: 106 additions & 0 deletions llvm/test/CodeGen/SPIRV/llvm-intrinsics/llround.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,106 @@
; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

@maarquitos14 please advise, which triple should be used for vulkan and opencl

Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Ideally, we should go with spirv64-unknown-unknown-opencl for opencl and spirv64-unknown-vulkan for vulkan.

Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Why vulkan is the OS component of the target triple, but OpenCL is the environment? I think they must be the same component.

Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I asked Google folks about that a while ago, this was their response:

To understand this part, we must look at the DXIL/HLSL triple:
HLSL uses the OS part to define the shader model, and the Env to define
the shader type. Example:

  - dxil-pc-shadermodel6.6-pixel
  - dxil-pc-shadermodel6.5-compute

So to have a similar model, we used the OS part for vulkan:
  - spirv-unknown-vulkan1.3-pixel
  - spirv-unknown-vulkan1.3-compute

If you switch vulkan to the environment, we would need to move the
pixel/compute/library/vertex to another part.

Regarding OpenCL, it was introduced as an environment for something completely unrelated to SPIRV.

Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

As I mentioned here, OpenCL should also be OS component.

Copy link
Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

How should I proceed with testing this intrinsic further?

Copy link
Contributor

@maarquitos14 maarquitos14 May 16, 2025 •
edited
Loading

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

As I mentioned here, OpenCL should also be OS component.

We are aware, @MrSidims asked the original author in #78655 (comment), but we had no answer yet. I can try and address that in a future PR, but for now, this is the current status of things.

Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I'm okay with cleaning things up in the future.
I interpreted Ideally in your previous comment as the current state of things doesn't require any improvements.

Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Ah, I see. I said ideally because for opencl spirv64-unknown-unknown should work, but I'd prefer to start having opencl explicitly in the triples, so that somebody reading the tests doesn't have to guess if it's intended for OpenCL or Vulkan. Sorry for the confusion.

; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}



Comment on lines +3 to +5
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Suggested change

; CHECK: [[opencl:%[0-9]+]] = OpExtInstImport "OpenCL.std"
; CHECK-DAG: [[f32:%[0-9]+]] = OpTypeFloat 32
; CHECK-DAG: [[i32:%[0-9]+]] = OpTypeInt 32 0
; CHECK-DAG: [[f64:%[0-9]+]] = OpTypeFloat 64
; CHECK-DAG: [[i64:%[0-9]+]] = OpTypeInt 64 0
; CHECK-DAG: [[vecf32:%[0-9]+]] = OpTypeVector [[f32]]
; CHECK-DAG: [[veci32:%[0-9]+]] = OpTypeVector [[i32]]
; CHECK-DAG: [[vecf64:%[0-9]+]] = OpTypeVector [[f64]]
; CHECK-DAG: [[veci64:%[0-9]+]] = OpTypeVector [[i64]]

; CHECK: [[rounded_i32_f32:%[0-9]+]] = OpExtInst [[f32]] [[opencl]] round %[[#]]
; CHECK-NEXT: %[[#]] = OpConvertFToS [[i32]] [[rounded_i32_f32]]
; CHECK: [[rounded_i32_f64:%[0-9]+]] = OpExtInst [[f64]] [[opencl]] round %[[#]]
; CHECK-NEXT: %[[#]] = OpConvertFToS [[i32]] [[rounded_i32_f64]]
; CHECK: [[rounded_i64_f32:%[0-9]+]] = OpExtInst [[f32]] [[opencl]] round %[[#]]
; CHECK-NEXT: %[[#]] = OpConvertFToS [[i64]] [[rounded_i64_f32]]
; CHECK: [[rounded_i64_f64:%[0-9]+]] = OpExtInst [[f64]] [[opencl]] round %[[#]]
; CHECK-NEXT: %[[#]] = OpConvertFToS [[i64]] [[rounded_i64_f64]]
; CHECK: [[rounded_v4i32_f32:%[0-9]+]] = OpExtInst [[vecf32]] [[opencl]] round %[[#]]
; CHECK-NEXT: %[[#]] = OpConvertFToS [[veci32]] [[rounded_v4i32_f32]]
; CHECK: [[rounded_v4i32_f64:%[0-9]+]] = OpExtInst [[vecf64]] [[opencl]] round %[[#]]
; CHECK-NEXT: %[[#]] = OpConvertFToS [[veci32]] [[rounded_v4i32_f64]]
; CHECK: [[rounded_v4i64_f32:%[0-9]+]] = OpExtInst [[vecf32]] [[opencl]] round %[[#]]
; CHECK-NEXT: %[[#]] = OpConvertFToS [[veci64]] [[rounded_v4i64_f32]]
; CHECK: [[rounded_v4i64_f64:%[0-9]+]] = OpExtInst [[vecf64]] [[opencl]] round %[[#]]
; CHECK-NEXT: %[[#]] = OpConvertFToS [[veci64]] [[rounded_v4i64_f64]]


define spir_func i32 @test_llround_i32_f32(float %arg0) {
entry:

Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

nit: please remove empty lines like this

%0 = call i32 @llvm.llround.i32.f32(float %arg0)
ret i32 %0
}

define spir_func i32 @test_llround_i32_f64(double %arg0) {
entry:


%0 = call i32 @llvm.llround.i32.f64(double %arg0)
ret i32 %0
}

define spir_func i64 @test_llround_i64_f32(float %arg0) {
entry:


%0 = call i64 @llvm.llround.i64.f32(float %arg0)
ret i64 %0
}

define spir_func i64 @test_llround_i64_f64(double %arg0) {
entry:


%0 = call i64 @llvm.llround.i64.f64(double %arg0)
ret i64 %0
}

define spir_func <4 x i32> @test_llround_v4i32_f32(<4 x float> %arg0) {
entry:


%0 = call <4 x i32> @llvm.llround.v4i32.f32(<4 x float> %arg0)
ret <4 x i32> %0
}


define spir_func <4 x i32> @test_llround_v4i32_f64(<4 x double> %arg0) {
entry:


%0 = call <4 x i32> @llvm.llround.v4i32.f64(<4 x double> %arg0)
ret <4 x i32> %0
}

define spir_func <4 x i64> @test_llround_v4i64_f32(<4 x float> %arg0) {
entry:


%0 = call <4 x i64> @llvm.llround.v4i64.f32(<4 x float> %arg0)
ret <4 x i64> %0
}


define spir_func <4 x i64> @test_llround_v4i64_f64(<4 x double> %arg0) {
entry:

%0 = call <4 x i64> @llvm.llround.v4i64.f64(<4 x double> %arg0)
ret <4 x i64> %0
}

declare i32 @llvm.llround.i32.f32(float)
declare i32 @llvm.llround.i32.f64(double)
declare i64 @llvm.llround.i64.f32(float)
declare i64 @llvm.llround.i64.f64(double)

declare <4 x i32> @llvm.llround.v4i32.f32(<4 x float>)
declare <4 x i32> @llvm.llround.v4i32.f64(<4 x double>)
declare <4 x i64> @llvm.llround.v4i64.f32(<4 x float>)
declare <4 x i64> @llvm.llround.v4i64.f64(<4 x double>)
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

lets remove EOF symbol

106 changes: 106 additions & 0 deletions llvm/test/CodeGen/SPIRV/llvm-intrinsics/lround.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,106 @@
; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}



; CHECK: [[opencl:%[0-9]+]] = OpExtInstImport "OpenCL.std"
; CHECK-DAG: [[f32:%[0-9]+]] = OpTypeFloat 32
; CHECK-DAG: [[i32:%[0-9]+]] = OpTypeInt 32 0
; CHECK-DAG: [[f64:%[0-9]+]] = OpTypeFloat 64
; CHECK-DAG: [[i64:%[0-9]+]] = OpTypeInt 64 0
; CHECK-DAG: [[vecf32:%[0-9]+]] = OpTypeVector [[f32]]
; CHECK-DAG: [[veci32:%[0-9]+]] = OpTypeVector [[i32]]
; CHECK-DAG: [[vecf64:%[0-9]+]] = OpTypeVector [[f64]]
; CHECK-DAG: [[veci64:%[0-9]+]] = OpTypeVector [[i64]]

; CHECK: [[rounded_i32_f32:%[0-9]+]] = OpExtInst [[f32]] [[opencl]] round %[[#]]
; CHECK-NEXT: %[[#]] = OpConvertFToS [[i32]] [[rounded_i32_f32]]
; CHECK: [[rounded_i32_f64:%[0-9]+]] = OpExtInst [[f64]] [[opencl]] round %[[#]]
; CHECK-NEXT: %[[#]] = OpConvertFToS [[i32]] [[rounded_i32_f64]]
; CHECK: [[rounded_i64_f32:%[0-9]+]] = OpExtInst [[f32]] [[opencl]] round %[[#]]
; CHECK-NEXT: %[[#]] = OpConvertFToS [[i64]] [[rounded_i64_f32]]
; CHECK: [[rounded_i64_f64:%[0-9]+]] = OpExtInst [[f64]] [[opencl]] round %[[#]]
; CHECK-NEXT: %[[#]] = OpConvertFToS [[i64]] [[rounded_i64_f64]]
; CHECK: [[rounded_v4i32_f32:%[0-9]+]] = OpExtInst [[vecf32]] [[opencl]] round %[[#]]
; CHECK-NEXT: %[[#]] = OpConvertFToS [[veci32]] [[rounded_v4i32_f32]]
; CHECK: [[rounded_v4i32_f64:%[0-9]+]] = OpExtInst [[vecf64]] [[opencl]] round %[[#]]
; CHECK-NEXT: %[[#]] = OpConvertFToS [[veci32]] [[rounded_v4i32_f64]]
; CHECK: [[rounded_v4i64_f32:%[0-9]+]] = OpExtInst [[vecf32]] [[opencl]] round %[[#]]
; CHECK-NEXT: %[[#]] = OpConvertFToS [[veci64]] [[rounded_v4i64_f32]]
; CHECK: [[rounded_v4i64_f64:%[0-9]+]] = OpExtInst [[vecf64]] [[opencl]] round %[[#]]
; CHECK-NEXT: %[[#]] = OpConvertFToS [[veci64]] [[rounded_v4i64_f64]]


define spir_func i32 @test_lround_i32_f32(float %arg0) {
entry:

%0 = call i32 @llvm.lround.i32.f32(float %arg0)
ret i32 %0
}

define spir_func i32 @test_lround_i32_f64(double %arg0) {
entry:


%0 = call i32 @llvm.lround.i32.f64(double %arg0)
ret i32 %0
}

define spir_func i64 @test_lround_i64_f32(float %arg0) {
entry:


%0 = call i64 @llvm.lround.i64.f32(float %arg0)
ret i64 %0
}

define spir_func i64 @test_lround_i64_f64(double %arg0) {
entry:


%0 = call i64 @llvm.lround.i64.f64(double %arg0)
ret i64 %0
}

define spir_func <4 x i32> @test_lround_v4i32_f32(<4 x float> %arg0) {
entry:


%0 = call <4 x i32> @llvm.lround.v4i32.f32(<4 x float> %arg0)
ret <4 x i32> %0
}


define spir_func <4 x i32> @test_lround_v4i32_f64(<4 x double> %arg0) {
entry:


%0 = call <4 x i32> @llvm.lround.v4i32.f64(<4 x double> %arg0)
ret <4 x i32> %0
}

define spir_func <4 x i64> @test_lround_v4i64_f32(<4 x float> %arg0) {
entry:


%0 = call <4 x i64> @llvm.lround.v4i64.f32(<4 x float> %arg0)
ret <4 x i64> %0
}


define spir_func <4 x i64> @test_lround_v4i64_f64(<4 x double> %arg0) {
entry:

%0 = call <4 x i64> @llvm.lround.v4i64.f64(<4 x double> %arg0)
ret <4 x i64> %0
}

declare i32 @llvm.lround.i32.f32(float)
declare i32 @llvm.lround.i32.f64(double)
declare i64 @llvm.lround.i64.f32(float)
declare i64 @llvm.lround.i64.f64(double)

declare <4 x i32> @llvm.lround.v4i32.f32(<4 x float>)
declare <4 x i32> @llvm.lround.v4i32.f64(<4 x double>)
declare <4 x i64> @llvm.lround.v4i64.f32(<4 x float>)
declare <4 x i64> @llvm.lround.v4i64.f64(<4 x double>)
Loading