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Reapply "[AArch64][SVE] Improve fixed-length addressing modes. (#130263)" #130625

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Mar 19, 2025
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9 changes: 3 additions & 6 deletions clang/test/CodeGen/AArch64/sve-vector-bits-codegen.c
Original file line number Diff line number Diff line change
Expand Up @@ -13,12 +13,9 @@

void func(int *restrict a, int *restrict b) {
// CHECK-LABEL: func
// CHECK256-COUNT-1: str
// CHECK256-COUNT-7: st1w
// CHECK512-COUNT-1: str
// CHECK512-COUNT-3: st1w
// CHECK1024-COUNT-1: str
// CHECK1024-COUNT-1: st1w
// CHECK256-COUNT-8: str
// CHECK512-COUNT-4: str
// CHECK1024-COUNT-2: str
// CHECK2048-COUNT-1: st1w
#pragma clang loop vectorize(enable)
for (int i = 0; i < 64; ++i)
Expand Down
38 changes: 32 additions & 6 deletions llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -7275,11 +7275,26 @@ static EVT getPackedVectorTypeFromPredicateType(LLVMContext &Ctx, EVT PredVT,
/// Return the EVT of the data associated to a memory operation in \p
/// Root. If such EVT cannot be retrived, it returns an invalid EVT.
static EVT getMemVTFromNode(LLVMContext &Ctx, SDNode *Root) {
if (isa<MemSDNode>(Root))
return cast<MemSDNode>(Root)->getMemoryVT();
if (auto *MemIntr = dyn_cast<MemIntrinsicSDNode>(Root))
return MemIntr->getMemoryVT();

if (isa<MemSDNode>(Root)) {
EVT MemVT = cast<MemSDNode>(Root)->getMemoryVT();

EVT DataVT;
if (auto *Load = dyn_cast<LoadSDNode>(Root))
DataVT = Load->getValueType(0);
else if (auto *Load = dyn_cast<MaskedLoadSDNode>(Root))
DataVT = Load->getValueType(0);
else if (auto *Store = dyn_cast<StoreSDNode>(Root))
DataVT = Store->getValue().getValueType();
else if (auto *Store = dyn_cast<MaskedStoreSDNode>(Root))
DataVT = Store->getValue().getValueType();
else
llvm_unreachable("Unexpected MemSDNode!");

if (isa<MemIntrinsicSDNode>(Root))
return cast<MemIntrinsicSDNode>(Root)->getMemoryVT();
return DataVT.changeVectorElementType(MemVT.getVectorElementType());
}

const unsigned Opcode = Root->getOpcode();
// For custom ISD nodes, we have to look at them individually to extract the
Expand Down Expand Up @@ -7380,12 +7395,23 @@ bool AArch64DAGToDAGISel::SelectAddrModeIndexedSVE(SDNode *Root, SDValue N,
return false;

SDValue VScale = N.getOperand(1);
if (VScale.getOpcode() != ISD::VSCALE)
int64_t MulImm = std::numeric_limits<int64_t>::max();
if (VScale.getOpcode() == ISD::VSCALE) {
MulImm = cast<ConstantSDNode>(VScale.getOperand(0))->getSExtValue();
} else if (auto C = dyn_cast<ConstantSDNode>(VScale)) {
int64_t ByteOffset = C->getSExtValue();
const auto KnownVScale =
Subtarget->getSVEVectorSizeInBits() / AArch64::SVEBitsPerBlock;

if (!KnownVScale || ByteOffset % KnownVScale != 0)
return false;

MulImm = ByteOffset / KnownVScale;
} else
return false;

TypeSize TS = MemVT.getSizeInBits();
int64_t MemWidthBytes = static_cast<int64_t>(TS.getKnownMinValue()) / 8;
int64_t MulImm = cast<ConstantSDNode>(VScale.getOperand(0))->getSExtValue();

if ((MulImm % MemWidthBytes) != 0)
return false;
Expand Down
12 changes: 11 additions & 1 deletion llvm/lib/Target/AArch64/AArch64Subtarget.h
Original file line number Diff line number Diff line change
Expand Up @@ -391,7 +391,7 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo {
void mirFileLoaded(MachineFunction &MF) const override;

// Return the known range for the bit length of SVE data registers. A value
// of 0 means nothing is known about that particular limit beyong what's
// of 0 means nothing is known about that particular limit beyond what's
// implied by the architecture.
unsigned getMaxSVEVectorSizeInBits() const {
assert(isSVEorStreamingSVEAvailable() &&
Expand All @@ -405,6 +405,16 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo {
return MinSVEVectorSizeInBits;
}

// Return the known bit length of SVE data registers. A value of 0 means the
// length is unkown beyond what's implied by the architecture.
unsigned getSVEVectorSizeInBits() const {
assert(isSVEorStreamingSVEAvailable() &&
"Tried to get SVE vector length without SVE support!");
if (MinSVEVectorSizeInBits == MaxSVEVectorSizeInBits)
return MaxSVEVectorSizeInBits;
return 0;
}

bool useSVEForFixedLengthVectors() const {
if (!isSVEorStreamingSVEAvailable())
return false;
Expand Down
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