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[AArch64] Funnel Shift now uses rev32/rev64 instructions #136707

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Merged
merged 5 commits into from
Apr 23, 2025
Merged

[AArch64] Funnel Shift now uses rev32/rev64 instructions #136707

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e63d8ff
[AARch64] Funnel Shift now uses rev32/rev64 instructions
jyli0116 Apr 22, 2025
eb402d9
Minor and aesthetic changes based on PR comments
jyli0116 Apr 23, 2025
ac5d7a3
Minor spelling mistake
jyli0116 Apr 23, 2025
a73d763
Merge branch 'llvm:main' into fshl_to_REV_instr
jyli0116 Apr 23, 2025
fd9140a
Whitespace change
jyli0116 Apr 23, 2025
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11 changes: 11 additions & 0 deletions llvm/lib/Target/AArch64/AArch64InstrInfo.td
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Original file line number Diff line number Diff line change
Expand Up @@ -5688,6 +5688,17 @@ def : Pat<(v4i32 (bswap (v4i32 V128:$Rn))),
def : Pat<(v2i64 (bswap (v2i64 V128:$Rn))),
(v2i64 (REV64v16i8 (v2i64 V128:$Rn)))>;

// Patterns for funnel shifts to be matched to equivalent REV instructions
def : Pat<(v2i64 (or (v2i64 (AArch64vshl (v2i64 V128:$Rn), (i32 32))),
(v2i64 (AArch64vlshr (v2i64 V128:$Rn), (i32 32))))),
(v2i64 (REV64v4i32 (v2i64 V128:$Rn)))>;
def : Pat<(v4i32 (or (v4i32 (AArch64vshl (v4i32 V128:$Rn), (i32 16))),
(v4i32 (AArch64vlshr (v4i32 V128:$Rn), (i32 16))))),
(v4i32 (REV32v8i16 (v4i32 V128:$Rn)))>;
def : Pat<(v2i32 (or (v2i32 (AArch64vshl (v2i32 V64:$Rn), (i32 16))),
(v2i32 (AArch64vlshr (v2i32 V64:$Rn), (i32 16))))),
(v2i32 (REV32v4i16 (v2i32 V64:$Rn)))>;

//===----------------------------------------------------------------------===//
// Advanced SIMD three vector instructions.
//===----------------------------------------------------------------------===//
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50 changes: 50 additions & 0 deletions llvm/test/CodeGen/AArch64/fsh.ll
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Expand Up @@ -4506,3 +4506,53 @@ entry:
%d = call <2 x i128> @llvm.fshr(<2 x i128> %a, <2 x i128> %b, <2 x i128> <i128 3, i128 3>)
ret <2 x i128> %d
}



define <2 x i64> @fshl_to_rev2i64(<2 x i64> %r) {
; CHECK-SD-LABEL: fshl_to_rev2i64:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: rev64 v0.4s, v0.4s
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: fshl_to_rev2i64:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: shl v1.2d, v0.2d, #32
; CHECK-GI-NEXT: ushr v0.2d, v0.2d, #32
; CHECK-GI-NEXT: orr v0.16b, v1.16b, v0.16b
; CHECK-GI-NEXT: ret
%or = tail call <2 x i64> @llvm.fshl.v2i64(<2 x i64> %r, <2 x i64> %r, <2 x i64> splat (i64 32))
ret <2 x i64> %or
}

define <4 x i32> @fshl_to_rev4i32(<4 x i32> %r) {
; CHECK-SD-LABEL: fshl_to_rev4i32:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: rev32 v0.8h, v0.8h
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: fshl_to_rev4i32:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: shl v1.4s, v0.4s, #16
; CHECK-GI-NEXT: ushr v0.4s, v0.4s, #16
; CHECK-GI-NEXT: orr v0.16b, v1.16b, v0.16b
; CHECK-GI-NEXT: ret
%or = tail call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %r, <4 x i32> %r, <4 x i32> splat (i32 16))
ret <4 x i32> %or
}

define <2 x i32> @fshl_to_rev2i32(<2 x i32> %r) {
; CHECK-SD-LABEL: fshl_to_rev2i32:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: rev32 v0.4h, v0.4h
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: fshl_to_rev2i32:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: shl v1.2s, v0.2s, #16
; CHECK-GI-NEXT: ushr v0.2s, v0.2s, #16
; CHECK-GI-NEXT: orr v0.8b, v1.8b, v0.8b
; CHECK-GI-NEXT: ret
%or = tail call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %r, <2 x i32> %r, <2 x i32> splat (i32 16))
ret <2 x i32> %or
}
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