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[Xtensa] Implement Xtensa S32C1I Option and atomics lowering. #137134

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[Xtensa] Implement Xtensa S32C1I Option and atomics lowering. #137134

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7 changes: 4 additions & 3 deletions llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -114,9 +114,10 @@ static DecodeStatus DecodeMR23RegisterClass(MCInst &Inst, uint64_t RegNo,
}

const MCPhysReg SRDecoderTable[] = {
Xtensa::SAR, 3, Xtensa::ACCLO, 16, Xtensa::ACCHI, 17,
Xtensa::M0, 32, Xtensa::M1, 33, Xtensa::M2, 34,
Xtensa::M3, 35, Xtensa::WINDOWBASE, 72, Xtensa::WINDOWSTART, 73};
Xtensa::SAR, 3, Xtensa::ACCLO, 16, Xtensa::ACCHI, 17,
Xtensa::SCOMPARE1, 12, Xtensa::M0, 32, Xtensa::M1, 33,
Xtensa::M2, 34, Xtensa::M3, 35, Xtensa::WINDOWBASE, 72,
Xtensa::WINDOWSTART, 73, Xtensa::ATOMCTL, 99};
Comment on lines +117 to +120
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I don't understand this table, it's mixed MCPhysReg and then a random number? Should this be some kind of pair or struct?


static DecodeStatus DecodeSRRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
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3 changes: 3 additions & 0 deletions llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp
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Expand Up @@ -86,6 +86,9 @@ bool Xtensa::checkRegister(MCRegister RegNo, const FeatureBitset &FeatureBits) {
case Xtensa::WINDOWBASE:
case Xtensa::WINDOWSTART:
return FeatureBits[Xtensa::FeatureWindowed];
case Xtensa::ATOMCTL:
case Xtensa::SCOMPARE1:
return FeatureBits[Xtensa::FeatureWindowed];
case Xtensa::NoRegister:
return false;
}
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16 changes: 16 additions & 0 deletions llvm/lib/Target/Xtensa/XtensaFeatures.td
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Expand Up @@ -67,3 +67,19 @@ def FeatureDiv32 : SubtargetFeature<"div32", "HasDiv32", "true",
"Enable Xtensa Div32 option">;
def HasDiv32 : Predicate<"Subtarget->hasDiv32()">,
AssemblerPredicate<(all_of FeatureDiv32)>;

def FeatureS32C1I : SubtargetFeature<"s32c1i", "HasS32C1I", "true",
"Enable Xtensa S32C1I option">;
def HasS32C1I : Predicate<"Subtarget->hasS32C1I()">,
AssemblerPredicate<(all_of FeatureS32C1I)>;

// Assume that lock-free native-width atomics are available, even if the target
// and operating system combination would not usually provide them. The user
// is responsible for providing any necessary __sync implementations. Code
// built with this feature is not ABI-compatible with code built without this
// feature, if atomic variables are exposed across the ABI boundary.
def FeatureForcedAtomics : SubtargetFeature<"forced-atomics", "HasForcedAtomics", "true",
"Assume that lock-free native-width atomics are available">;
def HasForcedAtomics : Predicate<"Subtarget->hasForcedAtomics()">,
AssemblerPredicate<(all_of FeatureForcedAtomics)>;
def HasAtomicLdSt : Predicate<"Subtarget->hasS32C1I() || Subtarget->hasForcedAtomics()">;
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