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[AMDGPU] Simplify getIns64. NFCI. #139981

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merged 1 commit into from
May 15, 2025
Merged

[AMDGPU] Simplify getIns64. NFCI. #139981

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94 changes: 19 additions & 75 deletions llvm/lib/Target/AMDGPU/SIInstrInfo.td
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Original file line number Diff line number Diff line change
Expand Up @@ -1972,81 +1972,25 @@ class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC,
RegisterOperand Src2RC, int NumSrcArgs,
bit HasClamp, bit HasModifiers, bit HasSrc2Mods, bit HasOMod,
Operand Src0Mod, Operand Src1Mod, Operand Src2Mod> {

dag ret =
!if (!eq(NumSrcArgs, 0),
// VOP1 without input operands (V_NOP, V_CLREXCP)
(ins),
/* else */
!if (!eq(NumSrcArgs, 1),
!if (HasModifiers,
// VOP1 with modifiers
!if(HasOMod,
(ins Src0Mod:$src0_modifiers, Src0RC:$src0,
Clamp0:$clamp, omod0:$omod),
!if (HasClamp,
(ins Src0Mod:$src0_modifiers, Src0RC:$src0, Clamp0:$clamp),
(ins Src0Mod:$src0_modifiers, Src0RC:$src0)))
/* else */,
// VOP1 without modifiers
!if(HasOMod,
(ins Src0RC:$src0, Clamp0:$clamp, omod0:$omod),
!if (HasClamp,
(ins Src0RC:$src0, Clamp0:$clamp),
(ins Src0RC:$src0)))
/* endif */ ),
!if (!eq(NumSrcArgs, 2),
!if (HasModifiers,
// VOP 2 with modifiers
!if(HasOMod,
(ins Src0Mod:$src0_modifiers, Src0RC:$src0,
Src1Mod:$src1_modifiers, Src1RC:$src1,
Clamp0:$clamp, omod0:$omod),
!con((ins Src0Mod:$src0_modifiers, Src0RC:$src0,
Src1Mod:$src1_modifiers, Src1RC:$src1),
!if(HasClamp, (ins Clamp0:$clamp), (ins))))
/* else */,
// VOP2 without modifiers
!if (HasClamp,
(ins Src0RC:$src0, Src1RC:$src1, Clamp0:$clamp),
(ins Src0RC:$src0, Src1RC:$src1))

/* endif */ )
/* NumSrcArgs == 3 */,
!if (HasModifiers,
!if (HasSrc2Mods,
// VOP3 with modifiers
!if (HasOMod,
(ins Src0Mod:$src0_modifiers, Src0RC:$src0,
Src1Mod:$src1_modifiers, Src1RC:$src1,
Src2Mod:$src2_modifiers, Src2RC:$src2,
Clamp0:$clamp, omod0:$omod),
!if (HasClamp,
(ins Src0Mod:$src0_modifiers, Src0RC:$src0,
Src1Mod:$src1_modifiers, Src1RC:$src1,
Src2Mod:$src2_modifiers, Src2RC:$src2,
Clamp0:$clamp),
(ins Src0Mod:$src0_modifiers, Src0RC:$src0,
Src1Mod:$src1_modifiers, Src1RC:$src1,
Src2Mod:$src2_modifiers, Src2RC:$src2))),
// VOP3 with modifiers except src2
!if (HasOMod,
(ins Src0Mod:$src0_modifiers, Src0RC:$src0,
Src1Mod:$src1_modifiers, Src1RC:$src1,
Src2RC:$src2, Clamp0:$clamp, omod0:$omod),
!if (HasClamp,
(ins Src0Mod:$src0_modifiers, Src0RC:$src0,
Src1Mod:$src1_modifiers, Src1RC:$src1,
Src2RC:$src2, Clamp0:$clamp),
(ins Src0Mod:$src0_modifiers, Src0RC:$src0,
Src1Mod:$src1_modifiers, Src1RC:$src1,
Src2RC:$src2))))
/* else */,
// VOP3 without modifiers
!if (HasClamp,
(ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2, Clamp0:$clamp),
(ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2))
/* endif */ ))));
dag src0 = !if(!ge(NumSrcArgs, 1),
!if (HasModifiers,
(ins Src0Mod:$src0_modifiers, Src0RC:$src0),
(ins Src0RC:$src0)),
(ins));
dag src1 = !if(!ge(NumSrcArgs, 2),
!if (HasModifiers,
(ins Src1Mod:$src1_modifiers, Src1RC:$src1),
(ins Src1RC:$src1)),
(ins));
dag src2 = !if(!ge(NumSrcArgs, 3),
!if (HasSrc2Mods,
(ins Src2Mod:$src2_modifiers, Src2RC:$src2),
(ins Src2RC:$src2)),
(ins));
dag clamp = !if(HasClamp, (ins Clamp0:$clamp), (ins));
dag omod = !if(HasOMod, (ins omod0:$omod), (ins));

dag ret = !con(src0, src1, src2, clamp, omod);
}

class getInsVOP3Base<RegisterOperand Src0RC, RegisterOperand Src1RC,
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/AMDGPU/VOP2Instructions.td
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Original file line number Diff line number Diff line change
Expand Up @@ -439,7 +439,7 @@ class VOP_MAC <ValueType vt0, ValueType vt1=vt0> : VOPProfile <[vt0, vt1, vt1, v
// Src2 must accept the same operand types as vdst, namely VGPRs only
let Src2RC64 = getVOP3VRegForVT<Src2VT, IsTrue16, !not(IsRealTrue16)>.ret;
let Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, 3,
0, HasModifiers, HasModifiers, HasOMod,
HasClamp, HasModifiers, HasModifiers, HasOMod,
Src0Mod, Src1Mod, Src2Mod>.ret;
let InsDPP = (ins Src0ModDPP:$src0_modifiers, Src0DPP:$src0,
Src1ModDPP:$src1_modifiers, Src1DPP:$src1,
Expand All @@ -448,7 +448,7 @@ class VOP_MAC <ValueType vt0, ValueType vt1=vt0> : VOPProfile <[vt0, vt1, vt1, v
DppBankMask:$bank_mask, DppBoundCtrl:$bound_ctrl);
let InsDPP16 = !con(InsDPP, (ins Dpp16FI:$fi));
let InsVOP3Base = getInsVOP3Base<Src0VOP3DPP, Src1VOP3DPP, RegisterOperand<VGPR_32>, 3,
0, HasModifiers, HasModifiers, HasOMod,
HasClamp, HasModifiers, HasModifiers, HasOMod,
Src0ModVOP3DPP, Src1ModVOP3DPP, Src2Mod, HasOpSel>.ret;
// We need a dummy src2 tied to dst to track the use of that register for s_delay_alu
let InsVOPDX = (ins Src0RC32:$src0X, Src1RC32:$vsrc1X, VGPRSrc_32:$src2X);
Expand Down