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[NVPTX] Prevent fptrunc of v2f32 from being folded into store #149571

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Merged
merged 3 commits into from
Jul 18, 2025
Merged

[NVPTX] Prevent fptrunc of v2f32 from being folded into store #149571

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9b6777c
pre-commit tests
AlexMaclean Jul 18, 2025
e092395
[NVPTX] Prevent fptrunc of v2f32 from being folded into store
AlexMaclean Jul 18, 2025
d7ae03f
fixup tests
AlexMaclean Jul 18, 2025
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2 changes: 2 additions & 0 deletions llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
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Expand Up @@ -731,6 +731,8 @@ NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM,
setTruncStoreAction(MVT::f32, MVT::bf16, Expand);
setTruncStoreAction(MVT::f64, MVT::bf16, Expand);
setTruncStoreAction(MVT::f64, MVT::f32, Expand);
setTruncStoreAction(MVT::v2f32, MVT::v2f16, Expand);
setTruncStoreAction(MVT::v2f32, MVT::v2bf16, Expand);

// PTX does not support load / store predicate registers
setOperationAction(ISD::LOAD, MVT::i1, Custom);
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7 changes: 4 additions & 3 deletions llvm/test/CodeGen/NVPTX/bf16x2-instructions.ll
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Expand Up @@ -359,11 +359,12 @@ define <2 x bfloat> @test_select_cc_bf16_f32(<2 x bfloat> %a, <2 x bfloat> %b,
define <2 x bfloat> @test_fptrunc_2xfloat(<2 x float> %a) #0 {
; CHECK-LABEL: test_fptrunc_2xfloat(
; CHECK: {
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-NEXT: .reg .b32 %r<4>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.b64 %rd1, [test_fptrunc_2xfloat_param_0];
; CHECK-NEXT: st.param.b32 [func_retval0], %rd1;
; CHECK-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_fptrunc_2xfloat_param_0];
; CHECK-NEXT: cvt.rn.bf16x2.f32 %r3, %r2, %r1;
; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
; CHECK-NEXT: ret;
%r = fptrunc <2 x float> %a to <2 x bfloat>
ret <2 x bfloat> %r
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9 changes: 7 additions & 2 deletions llvm/test/CodeGen/NVPTX/f16x2-instructions.ll
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Expand Up @@ -1433,11 +1433,16 @@ define <2 x half> @test_sitofp_2xi32_fadd(<2 x i32> %a, <2 x half> %b) #0 {
define <2 x half> @test_fptrunc_2xfloat(<2 x float> %a) #0 {
; CHECK-LABEL: test_fptrunc_2xfloat(
; CHECK: {
; CHECK-NEXT: .reg .b16 %rs<3>;
; CHECK-NEXT: .reg .b32 %r<4>;
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.b64 %rd1, [test_fptrunc_2xfloat_param_0];
; CHECK-NEXT: st.param.b32 [func_retval0], %rd1;
; CHECK-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_fptrunc_2xfloat_param_0];
; CHECK-NEXT: cvt.rn.f16.f32 %rs1, %r2;
; CHECK-NEXT: cvt.rn.f16.f32 %rs2, %r1;
; CHECK-NEXT: mov.b32 %r3, {%rs2, %rs1};
; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
; CHECK-NEXT: ret;
%r = fptrunc <2 x float> %a to <2 x half>
ret <2 x half> %r
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35 changes: 35 additions & 0 deletions llvm/test/CodeGen/NVPTX/f32x2-instructions.ll
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Expand Up @@ -1957,6 +1957,41 @@ define <2 x float> @test_uitofp_2xi32_to_2xfloat(<2 x i32> %a) #0 {
ret <2 x float> %r
}

define void @test_trunc_to_v2bf16(<2 x float> %a, ptr %p) {
; CHECK-LABEL: test_trunc_to_v2bf16(
; CHECK: {
; CHECK-NEXT: .reg .b32 %r<4>;
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.b64 %rd2, [test_trunc_to_v2bf16_param_1];
; CHECK-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_trunc_to_v2bf16_param_0];
; CHECK-NEXT: cvt.rn.bf16x2.f32 %r3, %r2, %r1;
; CHECK-NEXT: st.b32 [%rd2], %r3;
; CHECK-NEXT: ret;
%trunc = fptrunc <2 x float> %a to <2 x bfloat>
store <2 x bfloat> %trunc, ptr %p
ret void
}

define void @test_trunc_to_v2f16(<2 x float> %a, ptr %p) {
; CHECK-LABEL: test_trunc_to_v2f16(
; CHECK: {
; CHECK-NEXT: .reg .b32 %r<4>;
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.b64 %rd2, [test_trunc_to_v2f16_param_1];
; CHECK-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_trunc_to_v2f16_param_0];
; CHECK-NEXT: cvt.rn.f16x2.f32 %r3, %r2, %r1;
; CHECK-NEXT: st.b32 [%rd2], %r3;
; CHECK-NEXT: ret;
%trunc = fptrunc <2 x float> %a to <2 x half>
store <2 x half> %trunc, ptr %p
ret void
}


attributes #0 = { nounwind }
attributes #1 = { "unsafe-fp-math" = "true" }
attributes #2 = { "denormal-fp-math"="preserve-sign" }