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[RISCV] Fix VLOptimizer assert, relax ElementsDependOn on viota/vms{b,i,o}f.m #149698

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Merged
merged 1 commit into from
Jul 21, 2025
Merged

[RISCV] Fix VLOptimizer assert, relax ElementsDependOn on viota/vms{b,i,o}f.m #149698

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1 change: 1 addition & 0 deletions llvm/lib/Target/RISCV/RISCVInstrFormats.td
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Original file line number Diff line number Diff line change
Expand Up @@ -174,6 +174,7 @@ class EltDeps<bit vl, bit mask> {

def EltDepsNone : EltDeps<vl=0, mask=0>;
def EltDepsVL : EltDeps<vl=1, mask=0>;
def EltDepsMask : EltDeps<vl=0, mask=1>;
def EltDepsVLMask : EltDeps<vl=1, mask=1>;

class EEW <bits<2> val> {
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4 changes: 2 additions & 2 deletions llvm/lib/Target/RISCV/RISCVInstrInfoV.td
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Expand Up @@ -1642,7 +1642,7 @@ def VFIRST_M : RVInstV<0b010000, 0b10001, OPMVV, (outs GPR:$vd),

def : MnemonicAlias<"vpopc.m", "vcpop.m">;

let Constraints = "@earlyclobber $vd", RVVConstraint = Iota, ElementsDependOn = EltDepsVLMask in {
let Constraints = "@earlyclobber $vd", RVVConstraint = Iota, ElementsDependOn = EltDepsMask in {

let DestEEW = EEW1 in {
// vmsbf.m set-before-first mask bit
Expand All @@ -1655,7 +1655,7 @@ defm VMSOF_M : VMSFS_MV_V<"vmsof.m", 0b010100, 0b00010>;
// Vector Iota Instruction
defm VIOTA_M : VIOTA_MV_V<"viota.m", 0b010100, 0b10000>;

} // Constraints = "@earlyclobber $vd", RVVConstraint = Iota, ElementsDependOn = EltDepsVLMask
} // Constraints = "@earlyclobber $vd", RVVConstraint = Iota, ElementsDependOn = EltDepsMask

// Vector Element Index Instruction
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
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6 changes: 5 additions & 1 deletion llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
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Expand Up @@ -33,6 +33,7 @@ namespace {
class RISCVVLOptimizer : public MachineFunctionPass {
const MachineRegisterInfo *MRI;
const MachineDominatorTree *MDT;
const TargetInstrInfo *TII;

public:
static char ID;
Expand Down Expand Up @@ -1269,7 +1270,8 @@ bool RISCVVLOptimizer::isCandidate(const MachineInstr &MI) const {
return false;
}

assert(!RISCVII::elementsDependOnVL(RISCV::getRVVMCOpcode(MI.getOpcode())) &&
assert(!RISCVII::elementsDependOnVL(
TII->get(RISCV::getRVVMCOpcode(MI.getOpcode())).TSFlags) &&
"Instruction shouldn't be supported if elements depend on VL");

assert(MI.getOperand(0).isReg() &&
Expand Down Expand Up @@ -1473,6 +1475,8 @@ bool RISCVVLOptimizer::runOnMachineFunction(MachineFunction &MF) {
if (!ST.hasVInstructions())
return false;

TII = ST.getInstrInfo();

// For each instruction that defines a vector, compute what VL its
// downstream users demand.
for (MachineBasicBlock *MBB : post_order(&MF)) {
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