[AArch64][llvm] Fix disassembly of ldt{add,set,clr} instructions using xzr/wzr
#152292
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…ing `xzr/wzr`
The current disassembly of `ldt{add,set,clr}` instructions when using
`xzr/wzr` is incorrect. The Armv9.6-A Memory Systems specification says:
```
For each of LDT{ADD|SET|CLR}{L}, there is the corresponding STT{ADD|SET|CLR}{L}
alias, for the case where the register selected by the Rt field is XZR or WZR
```
and:
```
LDT{ADD|SET|CLR}{A}{L} is equivalent to LD{ADD|SET|CLR}{A}{L} except that: <..conditions..>
```
The Arm ARM specifies the preferred form of disassembly for these aliases:
```
STADD <Xs>, [<Xn|SP>]
is equivalent to
LDADD <Xs>, XZR, [<Xn|SP>]
and is always the preferred disassembly.
```
(DDI 0487L.b C6-2317)
This means that `sttadd` is the preferred disassembly for `ldtadd w0, wzr, [x2]`
when Rt is `xzr` or `wzr`.
This change also aligns llvm disassembly with GNU binutils, as shown by
the following examples:
llvm before this change:
```
% cat test.s
stadd w0, [sp]
sttadd w0, [sp]
ldadd w0, wzr, [sp]
ldtadd w0, wzr, [sp]
% llvm-mc-20 -triple aarch64 -mattr=+lse,+lsui test.s
stadd w0, [sp]
ldtadd w0, wzr, [sp]
stadd w0, [sp]
ldtadd w0, wzr, [sp]
```
llvm after this change:
```
% llvm-mc -triple aarch64 -mattr=+lse,+lsui test.s
stadd w0, [sp]
sttadd w0, [sp]
stadd w0, [sp]
sttadd w0, [sp]
```
GCC-15 test:
```
% gas test.s -march=armv8-a+lsui+lse -o test.o
% objdump -dr test.o
0: b82003ff stadd w0, [sp]
4: 192007ff sttadd w0, [sp]
8: b82003ff stadd w0, [sp]
c: 192007ff sttadd w0, [sp]
```
Many thanks to Ezra Sitorus and Alice Carlotti for reporting and
confirming this issue.
|
@llvm/pr-subscribers-mc Author: Jonathan Thackray (jthackray) ChangesThe current disassembly of and: The Arm ARM specifies the preferred form of disassembly for these aliases: (DDI 0487L.b C6-2317) This means that This change also aligns llvm disassembly with GNU binutils, as shown by the following examples: llvm before this change: llvm after this change: GCC-15 test: Many thanks to Ezra Sitorus and Alice Carlotti for reporting and confirming this issue. Full diff: https://github.com/llvm/llvm-project/pull/152292.diff 3 Files Affected:
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index 5a537f227760f..d068a12c7f7d5 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -12564,7 +12564,7 @@ multiclass STOPregister<string asm, string instr> {
let Predicates = [HasLSUI] in
class BaseSTOPregisterLSUI<string asm, RegisterClass OP, Register Reg,
Instruction inst> :
- InstAlias<asm # "\t$Rs, [$Rn]", (inst Reg, OP:$Rs, GPR64sp:$Rn), 0>;
+ InstAlias<asm # "\t$Rs, [$Rn]", (inst Reg, OP:$Rs, GPR64sp:$Rn)>;
multiclass STOPregisterLSUI<string asm, string instr> {
def : BaseSTOPregisterLSUI<asm # "l", GPR32, WZR,
diff --git a/llvm/test/MC/AArch64/armv9.6a-lsui.s b/llvm/test/MC/AArch64/armv9.6a-lsui.s
index d4a5e1f980560..dcd2693d0a021 100644
--- a/llvm/test/MC/AArch64/armv9.6a-lsui.s
+++ b/llvm/test/MC/AArch64/armv9.6a-lsui.s
@@ -212,10 +212,10 @@ _func:
//------------------------------------------------------------------------------
ldtadd w7, wzr, [x5]
-// CHECK: ldtadd w7, wzr, [x5] // encoding: [0xbf,0x04,0x27,0x19]
+// CHECK: sttadd w7, [x5] // encoding: [0xbf,0x04,0x27,0x19]
// ERROR: instruction requires: lsui
ldtadd x9, xzr, [sp]
-// CHECK: ldtadd x9, xzr, [sp] // encoding: [0xff,0x07,0x29,0x59]
+// CHECK: sttadd x9, [sp] // encoding: [0xff,0x07,0x29,0x59]
// ERROR: instruction requires: lsui
ldtadda w7, wzr, [x5]
@@ -226,10 +226,10 @@ _func:
// ERROR: instruction requires: lsui
ldtaddl w7, wzr, [x5]
-// CHECK: ldtaddl w7, wzr, [x5] // encoding: [0xbf,0x04,0x67,0x19]
+// CHECK: sttaddl w7, [x5] // encoding: [0xbf,0x04,0x67,0x19]
// ERROR: instruction requires: lsui
ldtaddl x9, xzr, [sp]
-// CHECK: ldtaddl x9, xzr, [sp] // encoding: [0xff,0x07,0x69,0x59]
+// CHECK: sttaddl x9, [sp] // encoding: [0xff,0x07,0x69,0x59]
// ERROR: instruction requires: lsui
ldtaddal w7, wzr, [x5]
@@ -240,17 +240,17 @@ _func:
// ERROR: instruction requires: lsui
ldtclr w7, wzr, [x5]
-// CHECK: ldtclr w7, wzr, [x5] // encoding: [0xbf,0x14,0x27,0x19]
+// CHECK: sttclr w7, [x5] // encoding: [0xbf,0x14,0x27,0x19]
// ERROR: instruction requires: lsui
ldtclr x9, xzr, [sp]
-// CHECK: ldtclr x9, xzr, [sp] // encoding: [0xff,0x17,0x29,0x59]
+// CHECK: sttclr x9, [sp] // encoding: [0xff,0x17,0x29,0x59]
// ERROR: instruction requires: lsui
ldtclrl w7, wzr, [x5]
-// CHECK: ldtclrl w7, wzr, [x5] // encoding: [0xbf,0x14,0x67,0x19]
+// CHECK: sttclrl w7, [x5] // encoding: [0xbf,0x14,0x67,0x19]
// ERROR: instruction requires: lsui
ldtclrl x9, xzr, [sp]
-// CHECK: ldtclrl x9, xzr, [sp] // encoding: [0xff,0x17,0x69,0x59]
+// CHECK: sttclrl x9, [sp] // encoding: [0xff,0x17,0x69,0x59]
// ERROR: instruction requires: lsui
ldtclra w7, wzr, [x5]
@@ -268,17 +268,17 @@ _func:
// ERROR: instruction requires: lsui
ldtset w7, wzr, [x5]
-// CHECK: ldtset w7, wzr, [x5] // encoding: [0xbf,0x34,0x27,0x19]
+// CHECK: sttset w7, [x5] // encoding: [0xbf,0x34,0x27,0x19]
// ERROR: instruction requires: lsui
ldtset x9, xzr, [sp]
-// CHECK: ldtset x9, xzr, [sp] // encoding: [0xff,0x37,0x29,0x59]
+// CHECK: sttset x9, [sp] // encoding: [0xff,0x37,0x29,0x59]
// ERROR: instruction requires: lsui
ldtsetl w7, wzr, [x5]
-// CHECK: ldtsetl w7, wzr, [x5] // encoding: [0xbf,0x34,0x67,0x19]
+// CHECK: sttsetl w7, [x5] // encoding: [0xbf,0x34,0x67,0x19]
// ERROR: instruction requires: lsui
ldtsetl x9, xzr, [sp]
-// CHECK: ldtsetl x9, xzr, [sp] // encoding: [0xff,0x37,0x69,0x59]
+// CHECK: sttsetl x9, [sp] // encoding: [0xff,0x37,0x69,0x59]
// ERROR: instruction requires: lsui
ldtseta w7, wzr, [x5]
@@ -300,81 +300,81 @@ _func:
//------------------------------------------------------------------------------
sttadd w0, [x2]
-// CHECK: ldtadd w0, wzr, [x2] // encoding: [0x5f,0x04,0x20,0x19]
+// CHECK: sttadd w0, [x2] // encoding: [0x5f,0x04,0x20,0x19]
// ERROR: instruction requires: lsui
sttadd w2, [sp]
-// CHECK: ldtadd w2, wzr, [sp] // encoding: [0xff,0x07,0x22,0x19]
+// CHECK: sttadd w2, [sp] // encoding: [0xff,0x07,0x22,0x19]
// ERROR: instruction requires: lsui
sttadd x0, [x2]
-// CHECK: ldtadd x0, xzr, [x2] // encoding: [0x5f,0x04,0x20,0x59]
+// CHECK: sttadd x0, [x2] // encoding: [0x5f,0x04,0x20,0x59]
// ERROR: instruction requires: lsui
sttadd x2, [sp]
-// CHECK: ldtadd x2, xzr, [sp] // encoding: [0xff,0x07,0x22,0x59]
+// CHECK: sttadd x2, [sp] // encoding: [0xff,0x07,0x22,0x59]
// ERROR: instruction requires: lsui
sttaddl w0, [x2]
-// CHECK: ldtaddl w0, wzr, [x2] // encoding: [0x5f,0x04,0x60,0x19]
+// CHECK: sttaddl w0, [x2] // encoding: [0x5f,0x04,0x60,0x19]
// ERROR: instruction requires: lsui
sttaddl w2, [sp]
-// CHECK: ldtaddl w2, wzr, [sp] // encoding: [0xff,0x07,0x62,0x19]
+// CHECK: sttaddl w2, [sp] // encoding: [0xff,0x07,0x62,0x19]
// ERROR: instruction requires: lsui
sttaddl x0, [x2]
-// CHECK: ldtaddl x0, xzr, [x2] // encoding: [0x5f,0x04,0x60,0x59]
+// CHECK: sttaddl x0, [x2] // encoding: [0x5f,0x04,0x60,0x59]
// ERROR: instruction requires: lsui
sttaddl x2, [sp]
-// CHECK: ldtaddl x2, xzr, [sp] // encoding: [0xff,0x07,0x62,0x59]
+// CHECK: sttaddl x2, [sp] // encoding: [0xff,0x07,0x62,0x59]
// ERROR: instruction requires: lsui
sttclr w0, [x2]
-// CHECK: ldtclr w0, wzr, [x2] // encoding: [0x5f,0x14,0x20,0x19]
+// CHECK: sttclr w0, [x2] // encoding: [0x5f,0x14,0x20,0x19]
// ERROR: instruction requires: lsui
sttclr w2, [sp]
-// CHECK: ldtclr w2, wzr, [sp] // encoding: [0xff,0x17,0x22,0x19]
+// CHECK: sttclr w2, [sp] // encoding: [0xff,0x17,0x22,0x19]
// ERROR: instruction requires: lsui
sttclr x0, [x2]
-// CHECK: ldtclr x0, xzr, [x2] // encoding: [0x5f,0x14,0x20,0x59]
+// CHECK: sttclr x0, [x2] // encoding: [0x5f,0x14,0x20,0x59]
// ERROR: instruction requires: lsui
sttclr x2, [sp]
-// CHECK: ldtclr x2, xzr, [sp] // encoding: [0xff,0x17,0x22,0x59]
+// CHECK: sttclr x2, [sp] // encoding: [0xff,0x17,0x22,0x59]
// ERROR: instruction requires: lsui
sttclrl w0, [x2]
-// CHECK: ldtclrl w0, wzr, [x2] // encoding: [0x5f,0x14,0x60,0x19]
+// CHECK: sttclrl w0, [x2] // encoding: [0x5f,0x14,0x60,0x19]
// ERROR: instruction requires: lsui
sttclrl w2, [sp]
-// CHECK: ldtclrl w2, wzr, [sp] // encoding: [0xff,0x17,0x62,0x19]
+// CHECK: sttclrl w2, [sp] // encoding: [0xff,0x17,0x62,0x19]
// ERROR: instruction requires: lsui
sttclrl x0, [x2]
-// CHECK: ldtclrl x0, xzr, [x2] // encoding: [0x5f,0x14,0x60,0x59]
+// CHECK: sttclrl x0, [x2] // encoding: [0x5f,0x14,0x60,0x59]
// ERROR: instruction requires: lsui
sttclrl x2, [sp]
-// CHECK: ldtclrl x2, xzr, [sp] // encoding: [0xff,0x17,0x62,0x59]
+// CHECK: sttclrl x2, [sp] // encoding: [0xff,0x17,0x62,0x59]
// ERROR: instruction requires: lsui
sttset w0, [x2]
-// CHECK: ldtset w0, wzr, [x2] // encoding: [0x5f,0x34,0x20,0x19]
+// CHECK: sttset w0, [x2] // encoding: [0x5f,0x34,0x20,0x19]
// ERROR: instruction requires: lsui
sttset w2, [sp]
-// CHECK: ldtset w2, wzr, [sp] // encoding: [0xff,0x37,0x22,0x19]
+// CHECK: sttset w2, [sp] // encoding: [0xff,0x37,0x22,0x19]
// ERROR: instruction requires: lsui
sttset x0, [x2]
-// CHECK: ldtset x0, xzr, [x2] // encoding: [0x5f,0x34,0x20,0x59]
+// CHECK: sttset x0, [x2] // encoding: [0x5f,0x34,0x20,0x59]
// ERROR: instruction requires: lsui
sttset x2, [sp]
-// CHECK: ldtset x2, xzr, [sp] // encoding: [0xff,0x37,0x22,0x59]
+// CHECK: sttset x2, [sp] // encoding: [0xff,0x37,0x22,0x59]
// ERROR: instruction requires: lsui
sttsetl w0, [x2]
-// CHECK: ldtsetl w0, wzr, [x2] // encoding: [0x5f,0x34,0x60,0x19]
+// CHECK: sttsetl w0, [x2] // encoding: [0x5f,0x34,0x60,0x19]
// ERROR: instruction requires: lsui
sttsetl w2, [sp]
-// CHECK: ldtsetl w2, wzr, [sp] // encoding: [0xff,0x37,0x62,0x19]
+// CHECK: sttsetl w2, [sp] // encoding: [0xff,0x37,0x62,0x19]
// ERROR: instruction requires: lsui
sttsetl x0, [x2]
-// CHECK: ldtsetl x0, xzr, [x2] // encoding: [0x5f,0x34,0x60,0x59]
+// CHECK: sttsetl x0, [x2] // encoding: [0x5f,0x34,0x60,0x59]
// ERROR: instruction requires: lsui
sttsetl x2, [sp]
-// CHECK: ldtsetl x2, xzr, [sp] // encoding: [0xff,0x37,0x62,0x59]
+// CHECK: sttsetl x2, [sp] // encoding: [0xff,0x37,0x62,0x59]
// ERROR: instruction requires: lsui
//------------------------------------------------------------------------------
diff --git a/llvm/test/MC/Disassembler/AArch64/armv9.6a-lsui.txt b/llvm/test/MC/Disassembler/AArch64/armv9.6a-lsui.txt
index 4cde11f38dde1..dc53a0bfc30e4 100644
--- a/llvm/test/MC/Disassembler/AArch64/armv9.6a-lsui.txt
+++ b/llvm/test/MC/Disassembler/AArch64/armv9.6a-lsui.txt
@@ -249,75 +249,75 @@
# CHECK-NEXT: casplt x0, x1, x2, x3, [sp]
# CHECK-NEXT: caspalt x0, x1, x2, x3, [x4]
# CHECK-NEXT: caspalt x0, x1, x2, x3, [sp]
-# CHECK-NEXT: ldtadd w7, wzr, [x5]
-# CHECK-NEXT: ldtadd x9, xzr, [sp]
+# CHECK-NEXT: sttadd w7, [x5]
+# CHECK-NEXT: sttadd x9, [sp]
# CHECK-NEXT: ldtadda w7, wzr, [x5]
# CHECK-NEXT: ldtadda x9, xzr, [sp]
-# CHECK-NEXT: ldtaddl w7, wzr, [x5]
-# CHECK-NEXT: ldtaddl x9, xzr, [sp]
+# CHECK-NEXT: sttaddl w7, [x5]
+# CHECK-NEXT: sttaddl x9, [sp]
# CHECK-NEXT: ldtaddal w7, wzr, [x5]
# CHECK-NEXT: ldtaddal x9, xzr, [sp]
-# CHECK-NEXT: ldtclr w7, wzr, [x5]
-# CHECK-NEXT: ldtclr x9, xzr, [sp]
-# CHECK-NEXT: ldtclrl w7, wzr, [x5]
-# CHECK-NEXT: ldtclrl x9, xzr, [sp]
+# CHECK-NEXT: sttclr w7, [x5]
+# CHECK-NEXT: sttclr x9, [sp]
+# CHECK-NEXT: sttclrl w7, [x5]
+# CHECK-NEXT: sttclrl x9, [sp]
# CHECK-NEXT: ldtclra w7, wzr, [x5]
# CHECK-NEXT: ldtclra x9, xzr, [sp]
# CHECK-NEXT: ldtclral w7, wzr, [x5]
# CHECK-NEXT: ldtclral x9, xzr, [sp]
-# CHECK-NEXT: ldtset w7, wzr, [x5]
-# CHECK-NEXT: ldtset x9, xzr, [sp]
-# CHECK-NEXT: ldtsetl w7, wzr, [x5]
-# CHECK-NEXT: ldtsetl x9, xzr, [sp]
+# CHECK-NEXT: sttset w7, [x5]
+# CHECK-NEXT: sttset x9, [sp]
+# CHECK-NEXT: sttsetl w7, [x5]
+# CHECK-NEXT: sttsetl x9, [sp]
# CHECK-NEXT: ldtseta w7, wzr, [x5]
# CHECK-NEXT: ldtseta x9, xzr, [sp]
# CHECK-NEXT: ldtsetal w7, wzr, [x5]
# CHECK-NEXT: ldtsetal x9, xzr, [sp]
-# CHECK-NEXT: ldtadd w0, wzr, [x2]
-# CHECK-NEXT: ldtadd w2, wzr, [sp]
-# CHECK-NEXT: ldtadd x0, xzr, [x2]
-# CHECK-NEXT: ldtadd x2, xzr, [sp]
-# CHECK-NEXT: ldtadd w0, wzr, [x2]
-# CHECK-NEXT: ldtadd w2, wzr, [sp]
-# CHECK-NEXT: ldtadd x0, xzr, [x2]
-# CHECK-NEXT: ldtadd x2, xzr, [sp]
-# CHECK-NEXT: ldtadd w0, wzr, [x2]
-# CHECK-NEXT: ldtadd w2, wzr, [sp]
-# CHECK-NEXT: ldtadd x0, xzr, [x2]
-# CHECK-NEXT: ldtadd x2, xzr, [sp]
-# CHECK-NEXT: ldtadd w0, wzr, [x2]
-# CHECK-NEXT: ldtadd w2, wzr, [sp]
-# CHECK-NEXT: ldtadd x0, xzr, [x2]
-# CHECK-NEXT: ldtadd x2, xzr, [sp]
-# CHECK-NEXT: ldtclr w0, wzr, [x2]
-# CHECK-NEXT: ldtclr w2, wzr, [sp]
-# CHECK-NEXT: ldtclr x0, xzr, [x2]
-# CHECK-NEXT: ldtclr x2, xzr, [sp]
-# CHECK-NEXT: ldtclr w0, wzr, [x2]
-# CHECK-NEXT: ldtclr w2, wzr, [sp]
-# CHECK-NEXT: ldtclr x0, xzr, [x2]
-# CHECK-NEXT: ldtclr x2, xzr, [sp]
-# CHECK-NEXT: ldtclr w0, wzr, [x2]
-# CHECK-NEXT: ldtclr w2, wzr, [sp]
-# CHECK-NEXT: ldtclr x0, xzr, [x2]
-# CHECK-NEXT: ldtclr x2, xzr, [sp]
-# CHECK-NEXT: ldtclr w0, wzr, [x2]
-# CHECK-NEXT: ldtclr x2, xzr, [sp]
-# CHECK-NEXT: ldtclr x0, xzr, [x2]
-# CHECK-NEXT: ldtclr x2, xzr, [sp]
-# CHECK-NEXT: ldtset w0, wzr, [x2]
-# CHECK-NEXT: ldtset w2, wzr, [sp]
-# CHECK-NEXT: ldtset x0, xzr, [x2]
-# CHECK-NEXT: ldtset x2, xzr, [sp]
-# CHECK-NEXT: ldtset w0, wzr, [x2]
-# CHECK-NEXT: ldtset w2, wzr, [sp]
-# CHECK-NEXT: ldtset x0, xzr, [x2]
-# CHECK-NEXT: ldtset x2, xzr, [sp]
-# CHECK-NEXT: ldtset w0, wzr, [x2]
-# CHECK-NEXT: ldtset w2, wzr, [sp]
-# CHECK-NEXT: ldtset x0, xzr, [x2]
-# CHECK-NEXT: ldtset x2, xzr, [sp]
-# CHECK-NEXT: ldtset w0, wzr, [x2]
-# CHECK-NEXT: ldtset x2, xzr, [sp]
-# CHECK-NEXT: ldtset x0, xzr, [x2]
-# CHECK-NEXT: ldtset x2, xzr, [sp]
+# CHECK-NEXT: sttadd w0, [x2]
+# CHECK-NEXT: sttadd w2, [sp]
+# CHECK-NEXT: sttadd x0, [x2]
+# CHECK-NEXT: sttadd x2, [sp]
+# CHECK-NEXT: sttadd w0, [x2]
+# CHECK-NEXT: sttadd w2, [sp]
+# CHECK-NEXT: sttadd x0, [x2]
+# CHECK-NEXT: sttadd x2, [sp]
+# CHECK-NEXT: sttadd w0, [x2]
+# CHECK-NEXT: sttadd w2, [sp]
+# CHECK-NEXT: sttadd x0, [x2]
+# CHECK-NEXT: sttadd x2, [sp]
+# CHECK-NEXT: sttadd w0, [x2]
+# CHECK-NEXT: sttadd w2, [sp]
+# CHECK-NEXT: sttadd x0, [x2]
+# CHECK-NEXT: sttadd x2, [sp]
+# CHECK-NEXT: sttclr w0, [x2]
+# CHECK-NEXT: sttclr w2, [sp]
+# CHECK-NEXT: sttclr x0, [x2]
+# CHECK-NEXT: sttclr x2, [sp]
+# CHECK-NEXT: sttclr w0, [x2]
+# CHECK-NEXT: sttclr w2, [sp]
+# CHECK-NEXT: sttclr x0, [x2]
+# CHECK-NEXT: sttclr x2, [sp]
+# CHECK-NEXT: sttclr w0, [x2]
+# CHECK-NEXT: sttclr w2, [sp]
+# CHECK-NEXT: sttclr x0, [x2]
+# CHECK-NEXT: sttclr x2, [sp]
+# CHECK-NEXT: sttclr w0, [x2]
+# CHECK-NEXT: sttclr x2, [sp]
+# CHECK-NEXT: sttclr x0, [x2]
+# CHECK-NEXT: sttclr x2, [sp]
+# CHECK-NEXT: sttset w0, [x2]
+# CHECK-NEXT: sttset w2, [sp]
+# CHECK-NEXT: sttset x0, [x2]
+# CHECK-NEXT: sttset x2, [sp]
+# CHECK-NEXT: sttset w0, [x2]
+# CHECK-NEXT: sttset w2, [sp]
+# CHECK-NEXT: sttset x0, [x2]
+# CHECK-NEXT: sttset x2, [sp]
+# CHECK-NEXT: sttset w0, [x2]
+# CHECK-NEXT: sttset w2, [sp]
+# CHECK-NEXT: sttset x0, [x2]
+# CHECK-NEXT: sttset x2, [sp]
+# CHECK-NEXT: sttset w0, [x2]
+# CHECK-NEXT: sttset x2, [sp]
+# CHECK-NEXT: sttset x0, [x2]
+# CHECK-NEXT: sttset x2, [sp]
|
|
@llvm/pr-subscribers-backend-aarch64 Author: Jonathan Thackray (jthackray) ChangesThe current disassembly of and: The Arm ARM specifies the preferred form of disassembly for these aliases: (DDI 0487L.b C6-2317) This means that This change also aligns llvm disassembly with GNU binutils, as shown by the following examples: llvm before this change: llvm after this change: GCC-15 test: Many thanks to Ezra Sitorus and Alice Carlotti for reporting and confirming this issue. Full diff: https://github.com/llvm/llvm-project/pull/152292.diff 3 Files Affected:
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index 5a537f227760f..d068a12c7f7d5 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -12564,7 +12564,7 @@ multiclass STOPregister<string asm, string instr> {
let Predicates = [HasLSUI] in
class BaseSTOPregisterLSUI<string asm, RegisterClass OP, Register Reg,
Instruction inst> :
- InstAlias<asm # "\t$Rs, [$Rn]", (inst Reg, OP:$Rs, GPR64sp:$Rn), 0>;
+ InstAlias<asm # "\t$Rs, [$Rn]", (inst Reg, OP:$Rs, GPR64sp:$Rn)>;
multiclass STOPregisterLSUI<string asm, string instr> {
def : BaseSTOPregisterLSUI<asm # "l", GPR32, WZR,
diff --git a/llvm/test/MC/AArch64/armv9.6a-lsui.s b/llvm/test/MC/AArch64/armv9.6a-lsui.s
index d4a5e1f980560..dcd2693d0a021 100644
--- a/llvm/test/MC/AArch64/armv9.6a-lsui.s
+++ b/llvm/test/MC/AArch64/armv9.6a-lsui.s
@@ -212,10 +212,10 @@ _func:
//------------------------------------------------------------------------------
ldtadd w7, wzr, [x5]
-// CHECK: ldtadd w7, wzr, [x5] // encoding: [0xbf,0x04,0x27,0x19]
+// CHECK: sttadd w7, [x5] // encoding: [0xbf,0x04,0x27,0x19]
// ERROR: instruction requires: lsui
ldtadd x9, xzr, [sp]
-// CHECK: ldtadd x9, xzr, [sp] // encoding: [0xff,0x07,0x29,0x59]
+// CHECK: sttadd x9, [sp] // encoding: [0xff,0x07,0x29,0x59]
// ERROR: instruction requires: lsui
ldtadda w7, wzr, [x5]
@@ -226,10 +226,10 @@ _func:
// ERROR: instruction requires: lsui
ldtaddl w7, wzr, [x5]
-// CHECK: ldtaddl w7, wzr, [x5] // encoding: [0xbf,0x04,0x67,0x19]
+// CHECK: sttaddl w7, [x5] // encoding: [0xbf,0x04,0x67,0x19]
// ERROR: instruction requires: lsui
ldtaddl x9, xzr, [sp]
-// CHECK: ldtaddl x9, xzr, [sp] // encoding: [0xff,0x07,0x69,0x59]
+// CHECK: sttaddl x9, [sp] // encoding: [0xff,0x07,0x69,0x59]
// ERROR: instruction requires: lsui
ldtaddal w7, wzr, [x5]
@@ -240,17 +240,17 @@ _func:
// ERROR: instruction requires: lsui
ldtclr w7, wzr, [x5]
-// CHECK: ldtclr w7, wzr, [x5] // encoding: [0xbf,0x14,0x27,0x19]
+// CHECK: sttclr w7, [x5] // encoding: [0xbf,0x14,0x27,0x19]
// ERROR: instruction requires: lsui
ldtclr x9, xzr, [sp]
-// CHECK: ldtclr x9, xzr, [sp] // encoding: [0xff,0x17,0x29,0x59]
+// CHECK: sttclr x9, [sp] // encoding: [0xff,0x17,0x29,0x59]
// ERROR: instruction requires: lsui
ldtclrl w7, wzr, [x5]
-// CHECK: ldtclrl w7, wzr, [x5] // encoding: [0xbf,0x14,0x67,0x19]
+// CHECK: sttclrl w7, [x5] // encoding: [0xbf,0x14,0x67,0x19]
// ERROR: instruction requires: lsui
ldtclrl x9, xzr, [sp]
-// CHECK: ldtclrl x9, xzr, [sp] // encoding: [0xff,0x17,0x69,0x59]
+// CHECK: sttclrl x9, [sp] // encoding: [0xff,0x17,0x69,0x59]
// ERROR: instruction requires: lsui
ldtclra w7, wzr, [x5]
@@ -268,17 +268,17 @@ _func:
// ERROR: instruction requires: lsui
ldtset w7, wzr, [x5]
-// CHECK: ldtset w7, wzr, [x5] // encoding: [0xbf,0x34,0x27,0x19]
+// CHECK: sttset w7, [x5] // encoding: [0xbf,0x34,0x27,0x19]
// ERROR: instruction requires: lsui
ldtset x9, xzr, [sp]
-// CHECK: ldtset x9, xzr, [sp] // encoding: [0xff,0x37,0x29,0x59]
+// CHECK: sttset x9, [sp] // encoding: [0xff,0x37,0x29,0x59]
// ERROR: instruction requires: lsui
ldtsetl w7, wzr, [x5]
-// CHECK: ldtsetl w7, wzr, [x5] // encoding: [0xbf,0x34,0x67,0x19]
+// CHECK: sttsetl w7, [x5] // encoding: [0xbf,0x34,0x67,0x19]
// ERROR: instruction requires: lsui
ldtsetl x9, xzr, [sp]
-// CHECK: ldtsetl x9, xzr, [sp] // encoding: [0xff,0x37,0x69,0x59]
+// CHECK: sttsetl x9, [sp] // encoding: [0xff,0x37,0x69,0x59]
// ERROR: instruction requires: lsui
ldtseta w7, wzr, [x5]
@@ -300,81 +300,81 @@ _func:
//------------------------------------------------------------------------------
sttadd w0, [x2]
-// CHECK: ldtadd w0, wzr, [x2] // encoding: [0x5f,0x04,0x20,0x19]
+// CHECK: sttadd w0, [x2] // encoding: [0x5f,0x04,0x20,0x19]
// ERROR: instruction requires: lsui
sttadd w2, [sp]
-// CHECK: ldtadd w2, wzr, [sp] // encoding: [0xff,0x07,0x22,0x19]
+// CHECK: sttadd w2, [sp] // encoding: [0xff,0x07,0x22,0x19]
// ERROR: instruction requires: lsui
sttadd x0, [x2]
-// CHECK: ldtadd x0, xzr, [x2] // encoding: [0x5f,0x04,0x20,0x59]
+// CHECK: sttadd x0, [x2] // encoding: [0x5f,0x04,0x20,0x59]
// ERROR: instruction requires: lsui
sttadd x2, [sp]
-// CHECK: ldtadd x2, xzr, [sp] // encoding: [0xff,0x07,0x22,0x59]
+// CHECK: sttadd x2, [sp] // encoding: [0xff,0x07,0x22,0x59]
// ERROR: instruction requires: lsui
sttaddl w0, [x2]
-// CHECK: ldtaddl w0, wzr, [x2] // encoding: [0x5f,0x04,0x60,0x19]
+// CHECK: sttaddl w0, [x2] // encoding: [0x5f,0x04,0x60,0x19]
// ERROR: instruction requires: lsui
sttaddl w2, [sp]
-// CHECK: ldtaddl w2, wzr, [sp] // encoding: [0xff,0x07,0x62,0x19]
+// CHECK: sttaddl w2, [sp] // encoding: [0xff,0x07,0x62,0x19]
// ERROR: instruction requires: lsui
sttaddl x0, [x2]
-// CHECK: ldtaddl x0, xzr, [x2] // encoding: [0x5f,0x04,0x60,0x59]
+// CHECK: sttaddl x0, [x2] // encoding: [0x5f,0x04,0x60,0x59]
// ERROR: instruction requires: lsui
sttaddl x2, [sp]
-// CHECK: ldtaddl x2, xzr, [sp] // encoding: [0xff,0x07,0x62,0x59]
+// CHECK: sttaddl x2, [sp] // encoding: [0xff,0x07,0x62,0x59]
// ERROR: instruction requires: lsui
sttclr w0, [x2]
-// CHECK: ldtclr w0, wzr, [x2] // encoding: [0x5f,0x14,0x20,0x19]
+// CHECK: sttclr w0, [x2] // encoding: [0x5f,0x14,0x20,0x19]
// ERROR: instruction requires: lsui
sttclr w2, [sp]
-// CHECK: ldtclr w2, wzr, [sp] // encoding: [0xff,0x17,0x22,0x19]
+// CHECK: sttclr w2, [sp] // encoding: [0xff,0x17,0x22,0x19]
// ERROR: instruction requires: lsui
sttclr x0, [x2]
-// CHECK: ldtclr x0, xzr, [x2] // encoding: [0x5f,0x14,0x20,0x59]
+// CHECK: sttclr x0, [x2] // encoding: [0x5f,0x14,0x20,0x59]
// ERROR: instruction requires: lsui
sttclr x2, [sp]
-// CHECK: ldtclr x2, xzr, [sp] // encoding: [0xff,0x17,0x22,0x59]
+// CHECK: sttclr x2, [sp] // encoding: [0xff,0x17,0x22,0x59]
// ERROR: instruction requires: lsui
sttclrl w0, [x2]
-// CHECK: ldtclrl w0, wzr, [x2] // encoding: [0x5f,0x14,0x60,0x19]
+// CHECK: sttclrl w0, [x2] // encoding: [0x5f,0x14,0x60,0x19]
// ERROR: instruction requires: lsui
sttclrl w2, [sp]
-// CHECK: ldtclrl w2, wzr, [sp] // encoding: [0xff,0x17,0x62,0x19]
+// CHECK: sttclrl w2, [sp] // encoding: [0xff,0x17,0x62,0x19]
// ERROR: instruction requires: lsui
sttclrl x0, [x2]
-// CHECK: ldtclrl x0, xzr, [x2] // encoding: [0x5f,0x14,0x60,0x59]
+// CHECK: sttclrl x0, [x2] // encoding: [0x5f,0x14,0x60,0x59]
// ERROR: instruction requires: lsui
sttclrl x2, [sp]
-// CHECK: ldtclrl x2, xzr, [sp] // encoding: [0xff,0x17,0x62,0x59]
+// CHECK: sttclrl x2, [sp] // encoding: [0xff,0x17,0x62,0x59]
// ERROR: instruction requires: lsui
sttset w0, [x2]
-// CHECK: ldtset w0, wzr, [x2] // encoding: [0x5f,0x34,0x20,0x19]
+// CHECK: sttset w0, [x2] // encoding: [0x5f,0x34,0x20,0x19]
// ERROR: instruction requires: lsui
sttset w2, [sp]
-// CHECK: ldtset w2, wzr, [sp] // encoding: [0xff,0x37,0x22,0x19]
+// CHECK: sttset w2, [sp] // encoding: [0xff,0x37,0x22,0x19]
// ERROR: instruction requires: lsui
sttset x0, [x2]
-// CHECK: ldtset x0, xzr, [x2] // encoding: [0x5f,0x34,0x20,0x59]
+// CHECK: sttset x0, [x2] // encoding: [0x5f,0x34,0x20,0x59]
// ERROR: instruction requires: lsui
sttset x2, [sp]
-// CHECK: ldtset x2, xzr, [sp] // encoding: [0xff,0x37,0x22,0x59]
+// CHECK: sttset x2, [sp] // encoding: [0xff,0x37,0x22,0x59]
// ERROR: instruction requires: lsui
sttsetl w0, [x2]
-// CHECK: ldtsetl w0, wzr, [x2] // encoding: [0x5f,0x34,0x60,0x19]
+// CHECK: sttsetl w0, [x2] // encoding: [0x5f,0x34,0x60,0x19]
// ERROR: instruction requires: lsui
sttsetl w2, [sp]
-// CHECK: ldtsetl w2, wzr, [sp] // encoding: [0xff,0x37,0x62,0x19]
+// CHECK: sttsetl w2, [sp] // encoding: [0xff,0x37,0x62,0x19]
// ERROR: instruction requires: lsui
sttsetl x0, [x2]
-// CHECK: ldtsetl x0, xzr, [x2] // encoding: [0x5f,0x34,0x60,0x59]
+// CHECK: sttsetl x0, [x2] // encoding: [0x5f,0x34,0x60,0x59]
// ERROR: instruction requires: lsui
sttsetl x2, [sp]
-// CHECK: ldtsetl x2, xzr, [sp] // encoding: [0xff,0x37,0x62,0x59]
+// CHECK: sttsetl x2, [sp] // encoding: [0xff,0x37,0x62,0x59]
// ERROR: instruction requires: lsui
//------------------------------------------------------------------------------
diff --git a/llvm/test/MC/Disassembler/AArch64/armv9.6a-lsui.txt b/llvm/test/MC/Disassembler/AArch64/armv9.6a-lsui.txt
index 4cde11f38dde1..dc53a0bfc30e4 100644
--- a/llvm/test/MC/Disassembler/AArch64/armv9.6a-lsui.txt
+++ b/llvm/test/MC/Disassembler/AArch64/armv9.6a-lsui.txt
@@ -249,75 +249,75 @@
# CHECK-NEXT: casplt x0, x1, x2, x3, [sp]
# CHECK-NEXT: caspalt x0, x1, x2, x3, [x4]
# CHECK-NEXT: caspalt x0, x1, x2, x3, [sp]
-# CHECK-NEXT: ldtadd w7, wzr, [x5]
-# CHECK-NEXT: ldtadd x9, xzr, [sp]
+# CHECK-NEXT: sttadd w7, [x5]
+# CHECK-NEXT: sttadd x9, [sp]
# CHECK-NEXT: ldtadda w7, wzr, [x5]
# CHECK-NEXT: ldtadda x9, xzr, [sp]
-# CHECK-NEXT: ldtaddl w7, wzr, [x5]
-# CHECK-NEXT: ldtaddl x9, xzr, [sp]
+# CHECK-NEXT: sttaddl w7, [x5]
+# CHECK-NEXT: sttaddl x9, [sp]
# CHECK-NEXT: ldtaddal w7, wzr, [x5]
# CHECK-NEXT: ldtaddal x9, xzr, [sp]
-# CHECK-NEXT: ldtclr w7, wzr, [x5]
-# CHECK-NEXT: ldtclr x9, xzr, [sp]
-# CHECK-NEXT: ldtclrl w7, wzr, [x5]
-# CHECK-NEXT: ldtclrl x9, xzr, [sp]
+# CHECK-NEXT: sttclr w7, [x5]
+# CHECK-NEXT: sttclr x9, [sp]
+# CHECK-NEXT: sttclrl w7, [x5]
+# CHECK-NEXT: sttclrl x9, [sp]
# CHECK-NEXT: ldtclra w7, wzr, [x5]
# CHECK-NEXT: ldtclra x9, xzr, [sp]
# CHECK-NEXT: ldtclral w7, wzr, [x5]
# CHECK-NEXT: ldtclral x9, xzr, [sp]
-# CHECK-NEXT: ldtset w7, wzr, [x5]
-# CHECK-NEXT: ldtset x9, xzr, [sp]
-# CHECK-NEXT: ldtsetl w7, wzr, [x5]
-# CHECK-NEXT: ldtsetl x9, xzr, [sp]
+# CHECK-NEXT: sttset w7, [x5]
+# CHECK-NEXT: sttset x9, [sp]
+# CHECK-NEXT: sttsetl w7, [x5]
+# CHECK-NEXT: sttsetl x9, [sp]
# CHECK-NEXT: ldtseta w7, wzr, [x5]
# CHECK-NEXT: ldtseta x9, xzr, [sp]
# CHECK-NEXT: ldtsetal w7, wzr, [x5]
# CHECK-NEXT: ldtsetal x9, xzr, [sp]
-# CHECK-NEXT: ldtadd w0, wzr, [x2]
-# CHECK-NEXT: ldtadd w2, wzr, [sp]
-# CHECK-NEXT: ldtadd x0, xzr, [x2]
-# CHECK-NEXT: ldtadd x2, xzr, [sp]
-# CHECK-NEXT: ldtadd w0, wzr, [x2]
-# CHECK-NEXT: ldtadd w2, wzr, [sp]
-# CHECK-NEXT: ldtadd x0, xzr, [x2]
-# CHECK-NEXT: ldtadd x2, xzr, [sp]
-# CHECK-NEXT: ldtadd w0, wzr, [x2]
-# CHECK-NEXT: ldtadd w2, wzr, [sp]
-# CHECK-NEXT: ldtadd x0, xzr, [x2]
-# CHECK-NEXT: ldtadd x2, xzr, [sp]
-# CHECK-NEXT: ldtadd w0, wzr, [x2]
-# CHECK-NEXT: ldtadd w2, wzr, [sp]
-# CHECK-NEXT: ldtadd x0, xzr, [x2]
-# CHECK-NEXT: ldtadd x2, xzr, [sp]
-# CHECK-NEXT: ldtclr w0, wzr, [x2]
-# CHECK-NEXT: ldtclr w2, wzr, [sp]
-# CHECK-NEXT: ldtclr x0, xzr, [x2]
-# CHECK-NEXT: ldtclr x2, xzr, [sp]
-# CHECK-NEXT: ldtclr w0, wzr, [x2]
-# CHECK-NEXT: ldtclr w2, wzr, [sp]
-# CHECK-NEXT: ldtclr x0, xzr, [x2]
-# CHECK-NEXT: ldtclr x2, xzr, [sp]
-# CHECK-NEXT: ldtclr w0, wzr, [x2]
-# CHECK-NEXT: ldtclr w2, wzr, [sp]
-# CHECK-NEXT: ldtclr x0, xzr, [x2]
-# CHECK-NEXT: ldtclr x2, xzr, [sp]
-# CHECK-NEXT: ldtclr w0, wzr, [x2]
-# CHECK-NEXT: ldtclr x2, xzr, [sp]
-# CHECK-NEXT: ldtclr x0, xzr, [x2]
-# CHECK-NEXT: ldtclr x2, xzr, [sp]
-# CHECK-NEXT: ldtset w0, wzr, [x2]
-# CHECK-NEXT: ldtset w2, wzr, [sp]
-# CHECK-NEXT: ldtset x0, xzr, [x2]
-# CHECK-NEXT: ldtset x2, xzr, [sp]
-# CHECK-NEXT: ldtset w0, wzr, [x2]
-# CHECK-NEXT: ldtset w2, wzr, [sp]
-# CHECK-NEXT: ldtset x0, xzr, [x2]
-# CHECK-NEXT: ldtset x2, xzr, [sp]
-# CHECK-NEXT: ldtset w0, wzr, [x2]
-# CHECK-NEXT: ldtset w2, wzr, [sp]
-# CHECK-NEXT: ldtset x0, xzr, [x2]
-# CHECK-NEXT: ldtset x2, xzr, [sp]
-# CHECK-NEXT: ldtset w0, wzr, [x2]
-# CHECK-NEXT: ldtset x2, xzr, [sp]
-# CHECK-NEXT: ldtset x0, xzr, [x2]
-# CHECK-NEXT: ldtset x2, xzr, [sp]
+# CHECK-NEXT: sttadd w0, [x2]
+# CHECK-NEXT: sttadd w2, [sp]
+# CHECK-NEXT: sttadd x0, [x2]
+# CHECK-NEXT: sttadd x2, [sp]
+# CHECK-NEXT: sttadd w0, [x2]
+# CHECK-NEXT: sttadd w2, [sp]
+# CHECK-NEXT: sttadd x0, [x2]
+# CHECK-NEXT: sttadd x2, [sp]
+# CHECK-NEXT: sttadd w0, [x2]
+# CHECK-NEXT: sttadd w2, [sp]
+# CHECK-NEXT: sttadd x0, [x2]
+# CHECK-NEXT: sttadd x2, [sp]
+# CHECK-NEXT: sttadd w0, [x2]
+# CHECK-NEXT: sttadd w2, [sp]
+# CHECK-NEXT: sttadd x0, [x2]
+# CHECK-NEXT: sttadd x2, [sp]
+# CHECK-NEXT: sttclr w0, [x2]
+# CHECK-NEXT: sttclr w2, [sp]
+# CHECK-NEXT: sttclr x0, [x2]
+# CHECK-NEXT: sttclr x2, [sp]
+# CHECK-NEXT: sttclr w0, [x2]
+# CHECK-NEXT: sttclr w2, [sp]
+# CHECK-NEXT: sttclr x0, [x2]
+# CHECK-NEXT: sttclr x2, [sp]
+# CHECK-NEXT: sttclr w0, [x2]
+# CHECK-NEXT: sttclr w2, [sp]
+# CHECK-NEXT: sttclr x0, [x2]
+# CHECK-NEXT: sttclr x2, [sp]
+# CHECK-NEXT: sttclr w0, [x2]
+# CHECK-NEXT: sttclr x2, [sp]
+# CHECK-NEXT: sttclr x0, [x2]
+# CHECK-NEXT: sttclr x2, [sp]
+# CHECK-NEXT: sttset w0, [x2]
+# CHECK-NEXT: sttset w2, [sp]
+# CHECK-NEXT: sttset x0, [x2]
+# CHECK-NEXT: sttset x2, [sp]
+# CHECK-NEXT: sttset w0, [x2]
+# CHECK-NEXT: sttset w2, [sp]
+# CHECK-NEXT: sttset x0, [x2]
+# CHECK-NEXT: sttset x2, [sp]
+# CHECK-NEXT: sttset w0, [x2]
+# CHECK-NEXT: sttset w2, [sp]
+# CHECK-NEXT: sttset x0, [x2]
+# CHECK-NEXT: sttset x2, [sp]
+# CHECK-NEXT: sttset w0, [x2]
+# CHECK-NEXT: sttset x2, [sp]
+# CHECK-NEXT: sttset x0, [x2]
+# CHECK-NEXT: sttset x2, [sp]
|
jthackray
requested review from
kmclaughlin-arm,
Lukacma,
CarolineConcatto,
rgwott and
amilendra
|
LGTM |
rgwott
approved these changes
Aug 6, 2025
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The current disassembly of
ldt{add,set,clr}instructions when usingxzr/wzris incorrect. The Armv9.6-A Memory Systems specification says:and:
The Arm ARM specifies the preferred form of disassembly for these aliases:
(DDI 0487L.b C6-2317)
This means that
sttaddis the preferred disassembly forldtadd w0, wzr, [x2]when Rt isxzrorwzr.This change also aligns llvm disassembly with GNU binutils, as shown by the following examples:
llvm before this change:
llvm after this change:
GCC-15 test:
Many thanks to Ezra Sitorus and Alice Carlotti for reporting and confirming this issue.