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[SelectionDAG] Add f16 soft promotion for lrint and lround #152684

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[SelectionDAG] Add f16 soft promotion for lrint and lround #152684

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14 changes: 12 additions & 2 deletions llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -3737,10 +3737,20 @@ bool DAGTypeLegalizer::SoftPromoteHalfOperand(SDNode *N, unsigned OpNo) {
Res = SoftPromoteHalfOp_FAKE_USE(N, OpNo);
break;
case ISD::FCOPYSIGN: Res = SoftPromoteHalfOp_FCOPYSIGN(N, OpNo); break;
case ISD::FP_TO_SINT:
case ISD::FP_TO_UINT:
case ISD::LLRINT:
case ISD::LLROUND:
case ISD::LRINT:
case ISD::LROUND:
Comment on lines +3742 to +3745
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Test changes seem to only cover lrint and llrint, and not lround/llround

case ISD::STRICT_FP_TO_SINT:
case ISD::STRICT_FP_TO_UINT:
case ISD::FP_TO_SINT:
case ISD::FP_TO_UINT: Res = SoftPromoteHalfOp_FP_TO_XINT(N); break;
case ISD::STRICT_LLRINT:
case ISD::STRICT_LLROUND:
case ISD::STRICT_LRINT:
case ISD::STRICT_LROUND:
Comment on lines +3748 to +3751
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strict cases also not tested?

Res = SoftPromoteHalfOp_FP_TO_XINT(N);
break;
case ISD::FP_TO_SINT_SAT:
case ISD::FP_TO_UINT_SAT:
Res = SoftPromoteHalfOp_FP_TO_XINT_SAT(N); break;
Expand Down
15 changes: 9 additions & 6 deletions llvm/test/CodeGen/ARM/lrint-conv.ll
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@@ -1,12 +1,15 @@
; RUN: llc < %s -mtriple=arm-eabi -float-abi=soft | FileCheck %s --check-prefix=SOFTFP
; RUN: llc < %s -mtriple=arm-eabi -float-abi=hard | FileCheck %s --check-prefix=HARDFP

; FIXME: crash
; define i32 @testmswh_builtin(half %x) {
; entry:
; %0 = tail call i32 @llvm.lrint.i32.f16(half %x)
; ret i32 %0
; }
; SOFTFP-LABEL: testmswh_builtin:
; SOFTFP: bl lrintf
; HARDFP-LABEL: testmswh_builtin:
; HARDFP: bl lrintf
define i32 @testmswh_builtin(half %x) {
entry:
%0 = tail call i32 @llvm.lrint.i32.f16(half %x)
ret i32 %0
}

; SOFTFP-LABEL: testmsws_builtin:
; SOFTFP: bl lrintf
Expand Down
33 changes: 24 additions & 9 deletions llvm/test/CodeGen/LoongArch/lrint-conv.ll
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Expand Up @@ -5,16 +5,31 @@
; RUN: sed 's/ITy/i32/g' %s | llc -mtriple=loongarch64 | FileCheck %s --check-prefixes=LA64-I32
; RUN: sed 's/ITy/i64/g' %s | llc -mtriple=loongarch64 | FileCheck %s --check-prefixes=LA64-I64

; FIXME: crash
; define ITy @test_lrint_ixx_f16(half %x) nounwind {
; %res = tail call ITy @llvm.lrint.ITy.f16(half %x)
; ret ITy %res
; }
define ITy @test_lrint_ixx_f16(half %x) nounwind {
; LA32-LABEL: test_lrint_ixx_f16:
; LA32: bl lrintf
;
; LA64-I32-LABEL: test_lrint_ixx_f16:
; LA64-I32: pcaddu18i $ra, %call36(lrintf)
;
; LA64-I64-LABEL: test_lrint_ixx_f16:
; LA64-I64: pcaddu18i $t8, %call36(lrintf)
%res = tail call ITy @llvm.lrint.ITy.f16(half %x)
ret ITy %res
}

; define ITy @test_llrint_ixx_f16(half %x) nounwind {
; %res = tail call ITy @llvm.llrint.ITy.f16(half %x)
; ret ITy %res
; }
define ITy @test_llrint_ixx_f16(half %x) nounwind {
; LA32-LABEL: test_llrint_ixx_f16:
; LA32: bl llrintf
;
; LA64-I32-LABEL: test_llrint_ixx_f16:
; LA64-I32: pcaddu18i $ra, %call36(llrintf)
;
; LA64-I64-LABEL: test_llrint_ixx_f16:
; LA64-I64: pcaddu18i $t8, %call36(llrintf)
%res = tail call ITy @llvm.llrint.ITy.f16(half %x)
ret ITy %res
}

define ITy @test_lrint_ixx_f32(float %x) nounwind {
; LA32-LABEL: test_lrint_ixx_f32:
Expand Down
23 changes: 11 additions & 12 deletions llvm/test/CodeGen/Mips/llrint-conv.ll
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@@ -1,19 +1,18 @@
; RUN: llc < %s -mtriple=mips64el -mattr=+soft-float | FileCheck %s
; RUN: llc < %s -mtriple=mips -mattr=+soft-float | FileCheck %s

; FIXME: crash
; define signext i32 @testmswh(half %x) {
; entry:
; %0 = tail call i64 @llvm.llrint.i64.f16(half %x)
; %conv = trunc i64 %0 to i32
; ret i32 %conv
; }
define signext i32 @testmswh(half %x) {
entry:
%0 = tail call i64 @llvm.llrint.i64.f16(half %x)
%conv = trunc i64 %0 to i32
ret i32 %conv
}

; define i64 @testmsxh(half %x) {
; entry:
; %0 = tail call i64 @llvm.llrint.i64.f16(half %x)
; ret i64 %0
; }
define i64 @testmsxh(half %x) {
entry:
%0 = tail call i64 @llvm.llrint.i64.f16(half %x)
ret i64 %0
}

define signext i32 @testmsws(float %x) {
; CHECK-LABEL: testmsws:
Expand Down
27 changes: 15 additions & 12 deletions llvm/test/CodeGen/Mips/lrint-conv.ll
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@@ -1,19 +1,22 @@
; RUN: llc < %s -mtriple=mips64el -mattr=+soft-float | FileCheck %s
; RUN: llc < %s -mtriple=mips -mattr=+soft-float | FileCheck %s

; FIXME: crash
; define signext i32 @testmswh(half %x) {
; entry:
; %0 = tail call i64 @llvm.lrint.i64.f16(half %x)
; %conv = trunc i64 %0 to i32
; ret i32 %conv
; }
define signext i32 @testmswh(half %x) {
; CHECK-LABEL: testmswh:
; CHECK: jal lrintf
entry:
%0 = tail call i64 @llvm.lrint.i64.f16(half %x)
%conv = trunc i64 %0 to i32
ret i32 %conv
}

; define i64 @testmsxh(half %x) {
; entry:
; %0 = tail call i64 @llvm.lrint.i64.f16(half %x)
; ret i64 %0
; }
define i64 @testmsxh(half %x) {
; CHECK-LABEL: testmsxh:
; CHECK: jal lrintf
entry:
%0 = tail call i64 @llvm.lrint.i64.f16(half %x)
ret i64 %0
}

define signext i32 @testmsws(float %x) {
; CHECK-LABEL: testmsws:
Expand Down
25 changes: 18 additions & 7 deletions llvm/test/CodeGen/RISCV/lrint-conv.ll
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Expand Up @@ -5,14 +5,25 @@
; RUN: sed 's/ITy/i32/g' %s | llc -mtriple=riscv64 | FileCheck %s --check-prefixes=RV64
; RUN: sed 's/ITy/i64/g' %s | llc -mtriple=riscv64 | FileCheck %s --check-prefixes=RV64

; FIXME: crash
; define ITy @test_lrint_ixx_f16(half %x) nounwind {
; %res = tail call ITy @llvm.lrint.ITy.f16(half %x)
; }
define ITy @test_lrint_ixx_f16(half %x) nounwind {
; RV32-LABEL: test_lrint_ixx_f16:
; RV32: call lrintf
;
; RV64-LABEL: test_lrint_ixx_f16:
; RV64: call lrintf
%res = tail call ITy @llvm.lrint.ITy.f16(half %x)
ret ITy %res
}

; define ITy @test_llrint_ixx_f16(half %x) nounwind {
; %res = tail call ITy @llvm.llrint.ITy.f16(half %x)
; }
define ITy @test_llrint_ixx_f16(half %x) nounwind {
; RV32-LABEL: test_llrint_ixx_f16:
; RV32: call llrintf
;
; RV64-LABEL: test_llrint_ixx_f16:
; RV64: call llrintf
%res = tail call ITy @llvm.llrint.ITy.f16(half %x)
ret ITy %res
}

define ITy @test_lrint_ixx_f32(float %x) nounwind {
; RV32-LABEL: test_lrint_ixx_f32:
Expand Down
55 changes: 43 additions & 12 deletions llvm/test/CodeGen/X86/llrint-conv.ll
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Expand Up @@ -7,12 +7,44 @@
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=avx | FileCheck %s --check-prefixes=X64,X64-AVX
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=avx512f | FileCheck %s --check-prefixes=X64,X64-AVX

; FIXME: crash
; define i64 @test_llrint_i64_f16(half %x) nounwind {
; entry:
; %0 = tail call i64 @llvm.llrint.i64.f16(half %x)
; ret i64 %0
; }
define i64 @test_llrint_i64_f16(half %x) nounwind {
; X86-NOSSE-LABEL: test_llrint_i64_f16:
; X86-NOSSE: # %bb.0: # %entry
; X86-NOSSE-NEXT: pushl %eax
; X86-NOSSE-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X86-NOSSE-NEXT: movl %eax, (%esp)
; X86-NOSSE-NEXT: calll __extendhfsf2
; X86-NOSSE-NEXT: fstps (%esp)
; X86-NOSSE-NEXT: calll llrintf
; X86-NOSSE-NEXT: popl %ecx
; X86-NOSSE-NEXT: retl
;
; X86-SSE2-LABEL: test_llrint_i64_f16:
; X86-SSE2: # %bb.0: # %entry
; X86-SSE2-NEXT: pushl %eax
; X86-SSE2-NEXT: pinsrw $0, {{[0-9]+}}(%esp), %xmm0
; X86-SSE2-NEXT: pextrw $0, %xmm0, %eax
; X86-SSE2-NEXT: movw %ax, (%esp)
; X86-SSE2-NEXT: calll __extendhfsf2
; X86-SSE2-NEXT: fstps (%esp)
; X86-SSE2-NEXT: calll llrintf
; X86-SSE2-NEXT: popl %ecx
; X86-SSE2-NEXT: retl
;
; X64-SSE-LABEL: test_llrint_i64_f16:
; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: pushq %rax
; X64-SSE-NEXT: callq __extendhfsf2@PLT
; X64-SSE-NEXT: callq rintf@PLT
; X64-SSE-NEXT: callq __truncsfhf2@PLT
; X64-SSE-NEXT: callq __extendhfsf2@PLT
; X64-SSE-NEXT: cvttss2si %xmm0, %rax
; X64-SSE-NEXT: popq %rcx
; X64-SSE-NEXT: retq
entry:
%0 = tail call i64 @llvm.llrint.i64.f16(half %x)
ret i64 %0
}

define i64 @test_llrint_i64_f32(float %x) nounwind {
; X86-NOSSE-LABEL: test_llrint_i64_f32:
Expand Down Expand Up @@ -217,12 +249,11 @@ entry:
ret i64 %0
}

; FIXME: crash
; define i64 @test_llrint_i64_f16_strict(half %x) nounwind strictfp {
; entry:
; %0 = tail call i64 @llvm.experimental.constrained.llrint.i64.f16(half %x, metadata!"round.dynamic", metadata!"fpexcept.strict")
; ret i64 %0
; }
define i64 @test_llrint_i64_f16_strict(half %x) nounwind strictfp {
entry:
%0 = tail call i64 @llvm.experimental.constrained.llrint.i64.f16(half %x, metadata!"round.dynamic", metadata!"fpexcept.strict")
ret i64 %0
}

define i64 @test_llrint_i64_f32_strict(float %x) nounwind strictfp {
; X86-NOSSE-LABEL: test_llrint_i64_f32_strict:
Expand Down
18 changes: 8 additions & 10 deletions llvm/test/CodeGen/X86/llround-conv.ll
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Expand Up @@ -5,11 +5,10 @@
; RUN: llc < %s -mtriple=i686-linux-gnu -global-isel -global-isel-abort=1 | FileCheck %s --check-prefixes=GISEL-X86
; RUN: llc < %s -mtriple=x86_64-linux-gnu -global-isel -global-isel-abort=1 | FileCheck %s --check-prefixes=GISEL-X64

; FIXME: crash
; define i64 @test_llround_f16(half %x) nounwind {
; %conv = tail call i64 @llvm.llround.f16(half %x)
; ret i64 %conv
; }
define i64 @test_llround_f16(half %x) nounwind {
%conv = tail call i64 @llvm.llround.f16(half %x)
ret i64 %conv
}

define i64 @test_llround_f32(float %x) nounwind {
; X86-NOSSE-LABEL: test_llround_f32:
Expand Down Expand Up @@ -184,11 +183,10 @@ define i64 @test_llround_f128(fp128 %x) nounwind {
ret i64 %conv
}

; FIXME: crash
; define i64 @test_llround_i64_f16(half %x) nounwind {
; %conv = call i64 @llvm.llround.i64.f16(half %x)
; ret i64 %conv
; }
define i64 @test_llround_i64_f16(half %x) nounwind {
%conv = call i64 @llvm.llround.i64.f16(half %x)
ret i64 %conv
}

define i64 @test_llround_i64_f32(float %x) nounwind {
; X86-NOSSE-LABEL: test_llround_i64_f32:
Expand Down
19 changes: 8 additions & 11 deletions llvm/test/CodeGen/X86/lrint-conv-i32.ll
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Expand Up @@ -7,12 +7,10 @@
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=avx | FileCheck %s --check-prefixes=X64,X64-AVX
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=avx512f | FileCheck %s --check-prefixes=X64,X64-AVX

; FIXME: crash
; define i32 @test_lrint_i32_f16(half %x) nounwind {
; entry:
; %0 = tail call i32 @llvm.lrint.i32.f16(half %x)
; ret i32 %0
; }
define i32 @test_lrint_i32_f16(half %x) nounwind {
%conv = tail call i32 @llvm.lrint.i32.f16(half %x)
ret i32 %conv
}

define i32 @test_lrint_i32_f32(float %x) nounwind {
; X86-NOSSE-LABEL: test_lrint_i32_f32:
Expand Down Expand Up @@ -154,11 +152,10 @@ define i32 @test_lrint_i32_f128(fp128 %x) nounwind {
ret i32 %conv
}

; FIXME: crash
; define i32 @test_lrint_i32_f16_strict(half %x) nounwind strictfp {
; %conv = tail call i32 @llvm.experimental.constrained.lrint.i32.f16(half %x, metadata!"round.dynamic", metadata!"fpexcept.strict")
; ret i32 %conv
; }
define i32 @test_lrint_i32_f16_strict(half %x) nounwind strictfp {
%conv = tail call i32 @llvm.experimental.constrained.lrint.i32.f16(half %x, metadata!"round.dynamic", metadata!"fpexcept.strict")
ret i32 %conv
}

define i32 @test_lrint_i32_f32_strict(float %x) nounwind strictfp {
; X86-NOSSE-LABEL: test_lrint_i32_f32_strict:
Expand Down
18 changes: 8 additions & 10 deletions llvm/test/CodeGen/X86/lrint-conv-i64.ll
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Expand Up @@ -5,11 +5,10 @@
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=avx | FileCheck %s --check-prefixes=CHECK,AVX
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=avx512f | FileCheck %s --check-prefixes=CHECK,AVX

; FIXME: crash
; define i64 @test_lrint_i64_f16(half %x) nounwind {
; %conv = tail call i64 @llvm.lrint.i64.f16(half %x)
; ret i64 %conv
; }
define i64 @test_lrint_i64_f16(half %x) nounwind {
%conv = tail call i64 @llvm.lrint.i64.f16(half %x)
ret i64 %conv
}

define i64 @test_lrint_i64_f32(float %x) nounwind {
; X86-NOSSE-LABEL: test_lrint_i64_f32:
Expand Down Expand Up @@ -149,11 +148,10 @@ define i64 @test_lrint_i64_f128(fp128 %x) nounwind {
ret i64 %conv
}

; FIXME: crash
; define i64 @test_lrint_i64_f16_strict(half %x) nounwind {
; %conv = tail call i64 @llvm.experimental.constrained.lrint.i64.f16(half %x, metadata!"round.dynamic", metadata!"fpexcept.strict")
; ret i64 %conv
; }
define i64 @test_lrint_i64_f16_strict(half %x) nounwind {
%conv = tail call i64 @llvm.experimental.constrained.lrint.i64.f16(half %x, metadata!"round.dynamic", metadata!"fpexcept.strict")
ret i64 %conv
}

define i64 @test_lrint_i64_f32_strict(float %x) nounwind {
; X86-NOSSE-LABEL: test_lrint_i64_f32_strict:
Expand Down
9 changes: 4 additions & 5 deletions llvm/test/CodeGen/X86/lround-conv-i32.ll
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Expand Up @@ -5,11 +5,10 @@
; RUN: llc < %s -mtriple=i686-linux-gnu -global-isel -global-isel-abort=1 | FileCheck %s --check-prefixes=GISEL-X86
; RUN: llc < %s -mtriple=x86_64-linux-gnu -global-isel -global-isel-abort=1 | FileCheck %s --check-prefixes=GISEL-X64

; FIXME: crash
; define i32 @test_lround_i32_f16(half %x) nounwind {
; %conv = tail call i32 @llvm.lround.i32.f16(half %x)
; ret i32 %conv
; }
define i32 @test_lround_i32_f16(half %x) nounwind {
%conv = tail call i32 @llvm.lround.i32.f16(half %x)
ret i32 %conv
}

define i32 @test_lround_i32_f32(float %x) nounwind {
; X86-LABEL: test_lround_i32_f32:
Expand Down
11 changes: 5 additions & 6 deletions llvm/test/CodeGen/X86/lround-conv-i64.ll
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Expand Up @@ -5,12 +5,11 @@
; RUN: llc < %s -mtriple=i686-linux-gnu -global-isel -global-isel-abort=1 | FileCheck %s --check-prefixes=GISEL-X86
; RUN: llc < %s -mtriple=x86_64-linux-gnu -global-isel -global-isel-abort=1 | FileCheck %s --check-prefixes=GISEL-X64

; FIXME: crash
; define i64 @test_lround_i64_f16(half %x) nounwind {
; entry:
; %0 = tail call i64 @llvm.lround.i64.f16(half %x)
; ret i64 %0
; }
define i64 @test_lround_i64_f16(half %x) nounwind {
entry:
%0 = tail call i64 @llvm.lround.i64.f16(half %x)
ret i64 %0
}

define i64 @test_lround_i64_f32(float %x) nounwind {
; X86-NOSSE-LABEL: test_lround_i64_f32:
Expand Down
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