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[SelectionDAG] Add f16 soft promotion for lrint and lround #152684

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[SelectionDAG] Add f16 soft promotion for lrint and lround #152684

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17 changes: 14 additions & 3 deletions llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
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Expand Up @@ -20,6 +20,7 @@

#include "LegalizeTypes.h"
#include "llvm/Analysis/TargetLibraryInfo.h"
#include "llvm/CodeGen/ISDOpcodes.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
using namespace llvm;
Expand Down Expand Up @@ -3729,10 +3730,20 @@ bool DAGTypeLegalizer::SoftPromoteHalfOperand(SDNode *N, unsigned OpNo) {
Res = SoftPromoteHalfOp_FAKE_USE(N, OpNo);
break;
case ISD::FCOPYSIGN: Res = SoftPromoteHalfOp_FCOPYSIGN(N, OpNo); break;
case ISD::FP_TO_SINT:
case ISD::FP_TO_UINT:
case ISD::LLRINT:
case ISD::LLROUND:
case ISD::LRINT:
case ISD::LROUND:
Comment on lines +3735 to +3738
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Test changes seem to only cover lrint and llrint, and not lround/llround

case ISD::STRICT_FP_TO_SINT:
case ISD::STRICT_FP_TO_UINT:
case ISD::FP_TO_SINT:
case ISD::FP_TO_UINT: Res = SoftPromoteHalfOp_FP_TO_XINT(N); break;
case ISD::STRICT_LLRINT:
case ISD::STRICT_LLROUND:
case ISD::STRICT_LRINT:
case ISD::STRICT_LROUND:
Comment on lines +3741 to +3744
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strict cases also not tested?

Res = SoftPromoteHalfOp_UnaryOp(N);
break;
case ISD::FP_TO_SINT_SAT:
case ISD::FP_TO_UINT_SAT:
Res = SoftPromoteHalfOp_FP_TO_XINT_SAT(N); break;
Expand Down Expand Up @@ -3811,7 +3822,7 @@ SDValue DAGTypeLegalizer::SoftPromoteHalfOp_FP_EXTEND(SDNode *N) {
return DAG.getNode(GetPromotionOpcode(SVT, RVT), SDLoc(N), RVT, Op);
}

SDValue DAGTypeLegalizer::SoftPromoteHalfOp_FP_TO_XINT(SDNode *N) {
SDValue DAGTypeLegalizer::SoftPromoteHalfOp_UnaryOp(SDNode *N) {
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I think this provides the correct operation for l?l(rint|round), but I am not familiar enough with the code here to know for sure. So whoever is reviewing, please double check.

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I wouldn't name this UnaryOp - that implies it's an FP-to-FP same type operation which this is not

EVT RVT = N->getValueType(0);
bool IsStrict = N->isStrictFPOpcode();
SDValue Op = N->getOperand(IsStrict ? 1 : 0);
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
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Expand Up @@ -840,7 +840,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
SDValue SoftPromoteHalfOp_FAKE_USE(SDNode *N, unsigned OpNo);
SDValue SoftPromoteHalfOp_FCOPYSIGN(SDNode *N, unsigned OpNo);
SDValue SoftPromoteHalfOp_FP_EXTEND(SDNode *N);
SDValue SoftPromoteHalfOp_FP_TO_XINT(SDNode *N);
SDValue SoftPromoteHalfOp_UnaryOp(SDNode *N);
SDValue SoftPromoteHalfOp_FP_TO_XINT_SAT(SDNode *N);
SDValue SoftPromoteHalfOp_SETCC(SDNode *N);
SDValue SoftPromoteHalfOp_SELECT_CC(SDNode *N, unsigned OpNo);
Expand Down
15 changes: 9 additions & 6 deletions llvm/test/CodeGen/ARM/lrint-conv.ll
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@@ -1,12 +1,15 @@
; RUN: llc < %s -mtriple=arm-eabi -float-abi=soft | FileCheck %s --check-prefix=SOFTFP
; RUN: llc < %s -mtriple=arm-eabi -float-abi=hard | FileCheck %s --check-prefix=HARDFP

; FIXME: crash
; define i32 @testmswh_builtin(half %x) {
; entry:
; %0 = tail call i32 @llvm.lrint.i32.f16(half %x)
; ret i32 %0
; }
; SOFTFP-LABEL: testmswh_builtin:
; SOFTFP: bl lrintf
; HARDFP-LABEL: testmswh_builtin:
; HARDFP: bl lrintf
define i32 @testmswh_builtin(half %x) {
entry:
%0 = tail call i32 @llvm.lrint.i32.f16(half %x)
ret i32 %0
}

; SOFTFP-LABEL: testmsws_builtin:
; SOFTFP: bl lrintf
Expand Down
33 changes: 24 additions & 9 deletions llvm/test/CodeGen/LoongArch/lrint-conv.ll
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Expand Up @@ -5,16 +5,31 @@
; RUN: sed 's/ITy/i32/g' %s | llc -mtriple=loongarch64 | FileCheck %s --check-prefixes=LA64-I32
; RUN: sed 's/ITy/i64/g' %s | llc -mtriple=loongarch64 | FileCheck %s --check-prefixes=LA64-I64

; FIXME: crash
; define ITy @test_lrint_ixx_f16(half %x) nounwind {
; %res = tail call ITy @llvm.lrint.ITy.f16(half %x)
; ret ITy %res
; }
define ITy @test_lrint_ixx_f16(half %x) nounwind {
; LA32-LABEL: test_lrint_ixx_f16:
; LA32: bl lrintf
;
; LA64-I32-LABEL: test_lrint_ixx_f16:
; LA64-I32: pcaddu18i $ra, %call36(lrintf)
;
; LA64-I64-LABEL: test_lrint_ixx_f16:
; LA64-I64: pcaddu18i $t8, %call36(lrintf)
%res = tail call ITy @llvm.lrint.ITy.f16(half %x)
ret ITy %res
}

; define ITy @test_llrint_ixx_f16(half %x) nounwind {
; %res = tail call ITy @llvm.llrint.ITy.f16(half %x)
; ret ITy %res
; }
define ITy @test_llrint_ixx_f16(half %x) nounwind {
; LA32-LABEL: test_llrint_ixx_f16:
; LA32: bl llrintf
;
; LA64-I32-LABEL: test_llrint_ixx_f16:
; LA64-I32: pcaddu18i $ra, %call36(llrintf)
;
; LA64-I64-LABEL: test_llrint_ixx_f16:
; LA64-I64: pcaddu18i $t8, %call36(llrintf)
%res = tail call ITy @llvm.llrint.ITy.f16(half %x)
ret ITy %res
}

define ITy @test_lrint_ixx_f32(float %x) nounwind {
; LA32-LABEL: test_lrint_ixx_f32:
Expand Down
23 changes: 11 additions & 12 deletions llvm/test/CodeGen/Mips/llrint-conv.ll
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@@ -1,19 +1,18 @@
; RUN: llc < %s -mtriple=mips64el -mattr=+soft-float | FileCheck %s
; RUN: llc < %s -mtriple=mips -mattr=+soft-float | FileCheck %s

; FIXME: crash
; define signext i32 @testmswh(half %x) {
; entry:
; %0 = tail call i64 @llvm.llrint.i64.f16(half %x)
; %conv = trunc i64 %0 to i32
; ret i32 %conv
; }
define signext i32 @testmswh(half %x) {
entry:
%0 = tail call i64 @llvm.llrint.i64.f16(half %x)
%conv = trunc i64 %0 to i32
ret i32 %conv
}

; define i64 @testmsxh(half %x) {
; entry:
; %0 = tail call i64 @llvm.llrint.i64.f16(half %x)
; ret i64 %0
; }
define i64 @testmsxh(half %x) {
entry:
%0 = tail call i64 @llvm.llrint.i64.f16(half %x)
ret i64 %0
}

define signext i32 @testmsws(float %x) {
; CHECK-LABEL: testmsws:
Expand Down
27 changes: 15 additions & 12 deletions llvm/test/CodeGen/Mips/lrint-conv.ll
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@@ -1,19 +1,22 @@
; RUN: llc < %s -mtriple=mips64el -mattr=+soft-float | FileCheck %s
; RUN: llc < %s -mtriple=mips -mattr=+soft-float | FileCheck %s

; FIXME: crash
; define signext i32 @testmswh(half %x) {
; entry:
; %0 = tail call i64 @llvm.lrint.i64.f16(half %x)
; %conv = trunc i64 %0 to i32
; ret i32 %conv
; }
define signext i32 @testmswh(half %x) {
; CHECK-LABEL: testmswh:
; CHECK: jal lrintf
entry:
%0 = tail call i64 @llvm.lrint.i64.f16(half %x)
%conv = trunc i64 %0 to i32
ret i32 %conv
}

; define i64 @testmsxh(half %x) {
; entry:
; %0 = tail call i64 @llvm.lrint.i64.f16(half %x)
; ret i64 %0
; }
define i64 @testmsxh(half %x) {
; CHECK-LABEL: testmsxh:
; CHECK: jal lrintf
entry:
%0 = tail call i64 @llvm.lrint.i64.f16(half %x)
ret i64 %0
}

define signext i32 @testmsws(float %x) {
; CHECK-LABEL: testmsws:
Expand Down
25 changes: 18 additions & 7 deletions llvm/test/CodeGen/RISCV/lrint-conv.ll
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Expand Up @@ -5,14 +5,25 @@
; RUN: sed 's/ITy/i32/g' %s | llc -mtriple=riscv64 | FileCheck %s --check-prefixes=RV64
; RUN: sed 's/ITy/i64/g' %s | llc -mtriple=riscv64 | FileCheck %s --check-prefixes=RV64

; FIXME: crash
; define ITy @test_lrint_ixx_f16(half %x) nounwind {
; %res = tail call ITy @llvm.lrint.ITy.f16(half %x)
; }
define ITy @test_lrint_ixx_f16(half %x) nounwind {
; RV32-LABEL: test_lrint_ixx_f16:
; RV32: call lrintf
;
; RV64-LABEL: test_lrint_ixx_f16:
; RV64: call lrintf
%res = tail call ITy @llvm.lrint.ITy.f16(half %x)
ret ITy %res
}

; define ITy @test_llrint_ixx_f16(half %x) nounwind {
; %res = tail call ITy @llvm.llrint.ITy.f16(half %x)
; }
define ITy @test_llrint_ixx_f16(half %x) nounwind {
; RV32-LABEL: test_llrint_ixx_f16:
; RV32: call llrintf
;
; RV64-LABEL: test_llrint_ixx_f16:
; RV64: call llrintf
%res = tail call ITy @llvm.llrint.ITy.f16(half %x)
ret ITy %res
}

define ITy @test_lrint_ixx_f32(float %x) nounwind {
; RV32-LABEL: test_lrint_ixx_f32:
Expand Down
52 changes: 46 additions & 6 deletions llvm/test/CodeGen/X86/lrint-conv-i32.ll
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Expand Up @@ -7,12 +7,52 @@
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=avx | FileCheck %s --check-prefixes=X64,X64-AVX
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=avx512f | FileCheck %s --check-prefixes=X64,X64-AVX

; FIXME: crash
; define i32 @testmswh(half %x) nounwind {
; entry:
; %0 = tail call i32 @llvm.lrint.i32.f16(half %x)
; ret i32 %0
; }
define i32 @testmswh(half %x) nounwind {
; X86-NOSSE-LABEL: testmswh:
; X86-NOSSE: # %bb.0: # %entry
; X86-NOSSE-NEXT: pushl %eax
; X86-NOSSE-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X86-NOSSE-NEXT: pushl %eax
; X86-NOSSE-NEXT: calll __extendhfsf2
; X86-NOSSE-NEXT: addl $4, %esp
; X86-NOSSE-NEXT: fistpl (%esp)
; X86-NOSSE-NEXT: movl (%esp), %eax
; X86-NOSSE-NEXT: popl %ecx
; X86-NOSSE-NEXT: retl
;
; X86-SSE2-LABEL: testmswh:
; X86-SSE2: # %bb.0: # %entry
; X86-SSE2-NEXT: subl $8, %esp
; X86-SSE2-NEXT: pinsrw $0, {{[0-9]+}}(%esp), %xmm0
; X86-SSE2-NEXT: pextrw $0, %xmm0, %eax
; X86-SSE2-NEXT: movw %ax, (%esp)
; X86-SSE2-NEXT: calll __extendhfsf2
; X86-SSE2-NEXT: fstps (%esp)
; X86-SSE2-NEXT: calll rintf
; X86-SSE2-NEXT: fstps (%esp)
; X86-SSE2-NEXT: calll __truncsfhf2
; X86-SSE2-NEXT: pextrw $0, %xmm0, %eax
; X86-SSE2-NEXT: movw %ax, (%esp)
; X86-SSE2-NEXT: calll __extendhfsf2
; X86-SSE2-NEXT: fstps {{[0-9]+}}(%esp)
; X86-SSE2-NEXT: cvttss2si {{[0-9]+}}(%esp), %eax
; X86-SSE2-NEXT: addl $8, %esp
; X86-SSE2-NEXT: retl
;
; X64-SSE-LABEL: testmswh:
; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: pushq %rax
; X64-SSE-NEXT: callq __extendhfsf2@PLT
; X64-SSE-NEXT: callq rintf@PLT
; X64-SSE-NEXT: callq __truncsfhf2@PLT
; X64-SSE-NEXT: callq __extendhfsf2@PLT
; X64-SSE-NEXT: cvttss2si %xmm0, %eax
; X64-SSE-NEXT: popq %rcx
; X64-SSE-NEXT: retq
entry:
%0 = tail call i32 @llvm.lrint.i32.f16(half %x)
ret i32 %0
}

define i32 @testmsws(float %x) nounwind {
; X86-NOSSE-LABEL: testmsws:
Expand Down