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[LiveRegUnits] Exclude runtime defined liveins when computing liveouts #154325

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Merged
merged 4 commits into from
Aug 21, 2025
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[LiveRegUnits] Exclude runtime defined liveins when computing liveouts #154325

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e809e3b
[AArch64][SME] Exclude runtime defined liveins when computing liveouts
MacDue Aug 19, 2025
9f64b69
Use MBB.liveouts()
MacDue Aug 20, 2025
d970c10
Remove decl
MacDue Aug 20, 2025
836206b
Remove include
MacDue Aug 20, 2025
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4 changes: 2 additions & 2 deletions llvm/include/llvm/CodeGen/MachineBasicBlock.h
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Original file line number Diff line number Diff line change
Expand Up @@ -553,8 +553,8 @@ class MachineBasicBlock
LiveRegI = (*BlockI)->livein_begin();
if (!advanceToValidPosition())
return;
if (LiveRegI->PhysReg == ExceptionPointer ||
LiveRegI->PhysReg == ExceptionSelector)
if ((*BlockI)->isEHPad() && (LiveRegI->PhysReg == ExceptionPointer ||
LiveRegI->PhysReg == ExceptionSelector))
Comment on lines +556 to +557
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This was a latent bug, these registers should not be skipped outside of landing-pads (this matches the logic in operator++).

++(*this);
}
}
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13 changes: 8 additions & 5 deletions llvm/lib/CodeGen/LiveRegUnits.cpp
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Expand Up @@ -91,6 +91,13 @@ static void addBlockLiveIns(LiveRegUnits &LiveUnits,
LiveUnits.addRegMasked(LI.PhysReg, LI.LaneMask);
}

/// Add live-out registers of basic block \p MBB to \p LiveUnits.
static void addBlockLiveOuts(LiveRegUnits &LiveUnits,
const MachineBasicBlock &MBB) {
for (const auto &LI : MBB.liveouts())
LiveUnits.addRegMasked(LI.PhysReg, LI.LaneMask);
}

/// Adds all callee saved registers to \p LiveUnits.
static void addCalleeSavedRegs(LiveRegUnits &LiveUnits,
const MachineFunction &MF) {
Expand Down Expand Up @@ -137,12 +144,8 @@ void LiveRegUnits::addPristines(const MachineFunction &MF) {

void LiveRegUnits::addLiveOuts(const MachineBasicBlock &MBB) {
const MachineFunction &MF = *MBB.getParent();

addPristines(MF);

// To get the live-outs we simply merge the live-ins of all successors.
for (const MachineBasicBlock *Succ : MBB.successors())
addBlockLiveIns(*this, *Succ);
addBlockLiveOuts(*this, MBB);

// For the return block: Add all callee saved registers.
if (MBB.isReturnBlock()) {
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3 changes: 0 additions & 3 deletions llvm/lib/CodeGen/MachineBasicBlock.cpp
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Expand Up @@ -1781,9 +1781,6 @@ MachineBasicBlock::livein_iterator MachineBasicBlock::livein_begin() const {

MachineBasicBlock::liveout_iterator MachineBasicBlock::liveout_begin() const {
const MachineFunction &MF = *getParent();
assert(MF.getProperties().hasTracksLiveness() &&
"Liveness information is accurate");

Comment on lines -1784 to -1786
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Note: This assert occurs too early (so asserts for blocks with no successors), removing this is safe as the liveout_iterator internally calls livein_begin(), which contains the same assert.

const TargetLowering &TLI = *MF.getSubtarget().getTargetLowering();
MCRegister ExceptionPointer, ExceptionSelector;
if (MF.getFunction().hasPersonalityFn()) {
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82 changes: 82 additions & 0 deletions llvm/test/CodeGen/AArch64/sme-abi-eh-liveins.mir
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@@ -0,0 +1,82 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=aarch64 -mattr=+sve -mattr=+sme -run-pass=aarch64-machine-sme-abi -verify-machineinstrs %s -o - | FileCheck %s

# This test verifies that runtime defined live-ins are not included in the live
# outs of predecessors in the MachineSMEABIPass, as including them would result
# in copies of undefined registers.

--- |
define void @sme_abi_eh_liveins() "aarch64_inout_za" personality ptr @__gxx_personality_v0 { entry: unreachable }

declare i32 @__gxx_personality_v0(...)
...
---
name: sme_abi_eh_liveins
tracksRegLiveness: true
isSSA: true
noVRegs: false

body: |
; CHECK-LABEL: name: sme_abi_eh_liveins
; CHECK: bb.0:
; CHECK-NEXT: successors: %bb.2(0x00000000), %bb.1(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[RDSVLI_XI:%[0-9]+]]:gpr64 = RDSVLI_XI 1, implicit $vg
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $sp
; CHECK-NEXT: [[MSUBXrrr:%[0-9]+]]:gpr64 = MSUBXrrr [[RDSVLI_XI]], [[RDSVLI_XI]], [[COPY]]
; CHECK-NEXT: $sp = COPY [[MSUBXrrr]]
; CHECK-NEXT: STPXi [[MSUBXrrr]], [[RDSVLI_XI]], %stack.0, 0
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
; CHECK-NEXT: InOutZAUsePseudo
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
; CHECK-NEXT: [[ADDXri:%[0-9]+]]:gpr64sp = ADDXri %stack.0, 0, 0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY [[ADDXri]]
; CHECK-NEXT: MSR 56965, [[COPY1]]
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
; CHECK-NEXT: RequiresZASavePseudo
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
; CHECK-NEXT: MSRpstatesvcrImm1 2, 1, implicit-def $nzcv
; CHECK-NEXT: [[MRS:%[0-9]+]]:gpr64 = MRS 56965, implicit-def $nzcv
; CHECK-NEXT: $x0 = ADDXri %stack.0, 0, 0
; CHECK-NEXT: RestoreZAPseudo [[MRS]], $x0, &__arm_tpidr2_restore, csr_aarch64_sme_abi_support_routines_preservemost_from_x0
; CHECK-NEXT: MSR 56965, $xzr
; CHECK-NEXT: B %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1 (landing-pad):
; CHECK-NEXT: successors: %bb.2(0x80000000)
; CHECK-NEXT: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: MSRpstatesvcrImm1 2, 1, implicit-def $nzcv
; CHECK-NEXT: [[MRS1:%[0-9]+]]:gpr64 = MRS 56965, implicit-def $nzcv
; CHECK-NEXT: $x0 = ADDXri %stack.0, 0, 0
; CHECK-NEXT: RestoreZAPseudo [[MRS1]], $x0, &__arm_tpidr2_restore, csr_aarch64_sme_abi_support_routines_preservemost_from_x0
; CHECK-NEXT: MSR 56965, $xzr
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
; CHECK-NEXT: InOutZAUsePseudo
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
bb.0:
successors: %bb.2(0x00000000), %bb.1(0x80000000)

; Simulate shared ZA call
ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
InOutZAUsePseudo
ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp

; Simulate private ZA call at the end of the block
ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
RequiresZASavePseudo
ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp

B %bb.2

bb.1 (landing-pad):
liveins: $x0, $x1

; Simulate shared ZA call
ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
InOutZAUsePseudo
ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp

bb.2:
9 changes: 2 additions & 7 deletions llvm/test/CodeGen/AArch64/sme-za-exceptions.ll
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@@ -1,9 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -aarch64-new-sme-abi -verify-machineinstrs < %s | FileCheck %s

; FIXME: XFAILs until https://github.com/llvm/llvm-project/pull/154325
; XFAIL: *

; A simple EH test case that corresponds to the following C++ source:
;
; struct ZAResource {
Expand Down Expand Up @@ -65,16 +62,14 @@ define void @za_with_raii(i1 %fail) "aarch64_inout_za" personality ptr @__gxx_pe
; CHECK-NEXT: ldr x1, [x1, :got_lo12:typeinfo_for_char_const_ptr]
; CHECK-NEXT: bl __cxa_throw
; CHECK-NEXT: .Ltmp1:
; CHECK-NEXT: mov x8, x0
; CHECK-NEXT: smstart za
; CHECK-NEXT: mrs x9, TPIDR2_EL0
; CHECK-NEXT: mrs x8, TPIDR2_EL0
; CHECK-NEXT: sub x0, x29, #16
; CHECK-NEXT: cbnz x9, .LBB0_4
; CHECK-NEXT: cbnz x8, .LBB0_4
; CHECK-NEXT: // %bb.3: // %throw_exception
; CHECK-NEXT: bl __arm_tpidr2_restore
; CHECK-NEXT: .LBB0_4: // %throw_exception
; CHECK-NEXT: msr TPIDR2_EL0, xzr
; CHECK-NEXT: // kill: def $x0 killed $x8
; CHECK-NEXT: // %bb.5: // %throw_fail
; CHECK-NEXT: .LBB0_6: // %unwind_dtors
; CHECK-NEXT: .Ltmp2:
Expand Down