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ARM: Remove TRI argument from AddDReg #158228

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ARM: Remove TRI argument from AddDReg #158228

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86 changes: 43 additions & 43 deletions llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -929,15 +929,15 @@ ARMBaseInstrInfo::describeLoadedValue(const MachineInstr &MI,
return TargetInstrInfo::describeLoadedValue(MI, Reg);
}

const MachineInstrBuilder &
ARMBaseInstrInfo::AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
unsigned SubIdx, unsigned State,
const TargetRegisterInfo *TRI) const {
const MachineInstrBuilder &ARMBaseInstrInfo::AddDReg(MachineInstrBuilder &MIB,
unsigned Reg,
unsigned SubIdx,
unsigned State) const {
if (!SubIdx)
return MIB.addReg(Reg, State);

if (Register::isPhysicalRegister(Reg))
return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
return MIB.addReg(getRegisterInfo().getSubReg(Reg, SubIdx), State);
return MIB.addReg(Reg, State, SubIdx);
}

Expand Down Expand Up @@ -1011,8 +1011,8 @@ void ARMBaseInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
} else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
if (Subtarget.hasV5TEOps()) {
MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::STRD));
AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill));
AddDReg(MIB, SrcReg, ARM::gsub_1, 0);
MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO)
.add(predOps(ARMCC::AL));
} else {
Expand All @@ -1022,8 +1022,8 @@ void ARMBaseInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
.addFrameIndex(FI)
.addMemOperand(MMO)
.add(predOps(ARMCC::AL));
AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill));
AddDReg(MIB, SrcReg, ARM::gsub_1, 0);
}
} else
llvm_unreachable("Unknown reg class!");
Expand Down Expand Up @@ -1073,9 +1073,9 @@ void ARMBaseInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
.addFrameIndex(FI)
.add(predOps(ARMCC::AL))
.addMemOperand(MMO);
MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill));
MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0);
AddDReg(MIB, SrcReg, ARM::dsub_2, 0);
}
} else
llvm_unreachable("Unknown reg class!");
Expand Down Expand Up @@ -1105,10 +1105,10 @@ void ARMBaseInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
.addFrameIndex(FI)
.add(predOps(ARMCC::AL))
.addMemOperand(MMO);
MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill));
MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0);
MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0);
AddDReg(MIB, SrcReg, ARM::dsub_3, 0);
}
} else
llvm_unreachable("Unknown reg class!");
Expand All @@ -1125,14 +1125,14 @@ void ARMBaseInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
.addFrameIndex(FI)
.add(predOps(ARMCC::AL))
.addMemOperand(MMO);
MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI);
MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI);
MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI);
AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI);
MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill));
MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0);
MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0);
MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0);
MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0);
MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0);
MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0);
AddDReg(MIB, SrcReg, ARM::dsub_7, 0);
} else
llvm_unreachable("Unknown reg class!");
break;
Expand Down Expand Up @@ -1272,8 +1272,8 @@ void ARMBaseInstrInfo::loadRegFromStackSlot(

if (Subtarget.hasV5TEOps()) {
MIB = BuildMI(MBB, I, DL, get(ARM::LDRD));
AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead);
AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead);
MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO)
.add(predOps(ARMCC::AL));
} else {
Expand All @@ -1283,8 +1283,8 @@ void ARMBaseInstrInfo::loadRegFromStackSlot(
.addFrameIndex(FI)
.addMemOperand(MMO)
.add(predOps(ARMCC::AL));
MIB = AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
MIB = AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
MIB = AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead);
MIB = AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead);
}

if (DestReg.isPhysical())
Expand Down Expand Up @@ -1330,9 +1330,9 @@ void ARMBaseInstrInfo::loadRegFromStackSlot(
.addFrameIndex(FI)
.addMemOperand(MMO)
.add(predOps(ARMCC::AL));
MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead);
MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead);
MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead);
if (DestReg.isPhysical())
MIB.addReg(DestReg, RegState::ImplicitDefine);
}
Expand All @@ -1359,10 +1359,10 @@ void ARMBaseInstrInfo::loadRegFromStackSlot(
.addFrameIndex(FI)
.add(predOps(ARMCC::AL))
.addMemOperand(MMO);
MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead);
MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead);
MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead);
MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead);
if (DestReg.isPhysical())
MIB.addReg(DestReg, RegState::ImplicitDefine);
}
Expand All @@ -1380,14 +1380,14 @@ void ARMBaseInstrInfo::loadRegFromStackSlot(
.addFrameIndex(FI)
.add(predOps(ARMCC::AL))
.addMemOperand(MMO);
MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::DefineNoRead, TRI);
MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead, TRI);
MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead, TRI);
MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead, TRI);
MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead);
MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead);
MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead);
MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead);
MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::DefineNoRead);
MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead);
MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead);
MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead);
if (DestReg.isPhysical())
MIB.addReg(DestReg, RegState::ImplicitDefine);
} else
Expand Down
3 changes: 1 addition & 2 deletions llvm/lib/Target/ARM/ARMBaseInstrInfo.h
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Original file line number Diff line number Diff line change
Expand Up @@ -240,8 +240,7 @@ class ARMBaseInstrInfo : public ARMGenInstrInfo {
const MachineInstr &Orig) const override;

const MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
unsigned SubIdx, unsigned State,
const TargetRegisterInfo *TRI) const;
unsigned SubIdx, unsigned State) const;

bool produceSameValue(const MachineInstr &MI0, const MachineInstr &MI1,
const MachineRegisterInfo *MRI) const override;
Expand Down
8 changes: 4 additions & 4 deletions llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -197,8 +197,8 @@ void Thumb2InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
}

MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2STRDi8));
AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill));
AddDReg(MIB, SrcReg, ARM::gsub_1, 0);
MIB.addFrameIndex(FI).addImm(0).addMemOperand(MMO).add(predOps(ARMCC::AL));
return;
}
Expand Down Expand Up @@ -238,8 +238,8 @@ void Thumb2InstrInfo::loadRegFromStackSlot(
}

MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2LDRDi8));
AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead);
AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead);
MIB.addFrameIndex(FI).addImm(0).addMemOperand(MMO).add(predOps(ARMCC::AL));

if (DestReg.isPhysical())
Expand Down
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