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CodeGen: Remove TRI argument from reMaterialize #158229

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CodeGen: Remove TRI argument from reMaterialize #158229

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3 changes: 1 addition & 2 deletions llvm/include/llvm/CodeGen/TargetInstrInfo.h
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Expand Up @@ -431,8 +431,7 @@ class LLVM_ABI TargetInstrInfo : public MCInstrInfo {
/// SubIdx.
virtual void reMaterialize(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI, Register DestReg,
unsigned SubIdx, const MachineInstr &Orig,
const TargetRegisterInfo &TRI) const;
unsigned SubIdx, const MachineInstr &Orig) const;

/// Clones instruction or the whole instruction bundle \p Orig and
/// insert into \p MBB before \p InsertBefore. The target may update operands
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2 changes: 1 addition & 1 deletion llvm/lib/CodeGen/LiveRangeEdit.cpp
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Expand Up @@ -182,7 +182,7 @@ SlotIndex LiveRangeEdit::rematerializeAt(MachineBasicBlock &MBB,
bool Late, unsigned SubIdx,
MachineInstr *ReplaceIndexMI) {
assert(RM.OrigMI && "Invalid remat");
TII.reMaterialize(MBB, MI, DestReg, SubIdx, *RM.OrigMI, tri);
TII.reMaterialize(MBB, MI, DestReg, SubIdx, *RM.OrigMI);
// DestReg of the cloned instruction cannot be Dead. Set isDead of DestReg
// to false anyway in case the isDead flag of RM.OrigMI's dest register
// is true.
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2 changes: 1 addition & 1 deletion llvm/lib/CodeGen/MachineSink.cpp
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Expand Up @@ -569,7 +569,7 @@ bool MachineSinking::PerformSinkAndFold(MachineInstr &MI,
// Sink a copy of the instruction, replacing a COPY instruction.
MachineBasicBlock::iterator InsertPt = SinkDst->getIterator();
Register DstReg = SinkDst->getOperand(0).getReg();
TII->reMaterialize(*SinkDst->getParent(), InsertPt, DstReg, 0, MI, *TRI);
TII->reMaterialize(*SinkDst->getParent(), InsertPt, DstReg, 0, MI);
New = &*std::prev(InsertPt);
if (!New->getDebugLoc())
New->setDebugLoc(SinkDst->getDebugLoc());
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8 changes: 4 additions & 4 deletions llvm/lib/CodeGen/TargetInstrInfo.cpp
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Expand Up @@ -445,10 +445,10 @@ bool TargetInstrInfo::getStackSlotRange(const TargetRegisterClass *RC,
return true;
}

void TargetInstrInfo::reMaterialize(
MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register DestReg,
unsigned SubIdx, const MachineInstr &Orig,
const TargetRegisterInfo & /*Remove me*/) const {
void TargetInstrInfo::reMaterialize(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
Register DestReg, unsigned SubIdx,
const MachineInstr &Orig) const {
MachineInstr *MI = MBB.getParent()->CloneMachineInstr(&Orig);
MI->substituteRegister(MI->getOperand(0).getReg(), DestReg, SubIdx, TRI);
MBB.insert(I, MI);
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5 changes: 2 additions & 3 deletions llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
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Expand Up @@ -1891,7 +1891,7 @@ void PreRARematStage::rematerialize() {

// Rematerialize DefMI to its use block.
TII->reMaterialize(*InsertPos->getParent(), InsertPos, Reg,
AMDGPU::NoSubRegister, *DefMI, *DAG.TRI);
AMDGPU::NoSubRegister, *DefMI);
Remat.RematMI = &*std::prev(InsertPos);
DAG.LIS->InsertMachineInstrInMaps(*Remat.RematMI);

Expand Down Expand Up @@ -2043,8 +2043,7 @@ void PreRARematStage::finalizeGCNSchedStage() {
// Re-rematerialize MI at the end of its original region. Note that it may
// not be rematerialized exactly in the same position as originally within
// the region, but it should not matter much.
TII->reMaterialize(*MBB, InsertPos, Reg, AMDGPU::NoSubRegister, RematMI,
*DAG.TRI);
TII->reMaterialize(*MBB, InsertPos, Reg, AMDGPU::NoSubRegister, RematMI);
MachineInstr *NewMI = &*std::prev(InsertPos);
DAG.LIS->InsertMachineInstrInMaps(*NewMI);

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6 changes: 3 additions & 3 deletions llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
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Expand Up @@ -2548,8 +2548,8 @@ bool SIInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {

void SIInstrInfo::reMaterialize(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I, Register DestReg,
unsigned SubIdx, const MachineInstr &Orig,
const TargetRegisterInfo &RI) const {
unsigned SubIdx,
const MachineInstr &Orig) const {

// Try shrinking the instruction to remat only the part needed for current
// context.
Expand Down Expand Up @@ -2629,7 +2629,7 @@ void SIInstrInfo::reMaterialize(MachineBasicBlock &MBB,
break;
}

TargetInstrInfo::reMaterialize(MBB, I, DestReg, SubIdx, Orig, RI);
TargetInstrInfo::reMaterialize(MBB, I, DestReg, SubIdx, Orig);
}

std::pair<MachineInstr*, MachineInstr*>
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3 changes: 1 addition & 2 deletions llvm/lib/Target/AMDGPU/SIInstrInfo.h
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Expand Up @@ -316,8 +316,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {

void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
Register DestReg, unsigned SubIdx,
const MachineInstr &Orig,
const TargetRegisterInfo &TRI) const override;
const MachineInstr &Orig) const override;

// Splits a V_MOV_B64_DPP_PSEUDO opcode into a pair of v_mov_b32_dpp
// instructions. Returns a pair of generated instructions.
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3 changes: 1 addition & 2 deletions llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
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Expand Up @@ -1653,8 +1653,7 @@ static unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) {
void ARMBaseInstrInfo::reMaterialize(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
Register DestReg, unsigned SubIdx,
const MachineInstr &Orig,
const TargetRegisterInfo &TRI) const {
const MachineInstr &Orig) const {
unsigned Opcode = Orig.getOpcode();
switch (Opcode) {
default: {
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3 changes: 1 addition & 2 deletions llvm/lib/Target/ARM/ARMBaseInstrInfo.h
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Expand Up @@ -232,8 +232,7 @@ class ARMBaseInstrInfo : public ARMGenInstrInfo {

void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
Register DestReg, unsigned SubIdx,
const MachineInstr &Orig,
const TargetRegisterInfo &TRI) const override;
const MachineInstr &Orig) const override;

MachineInstr &
duplicate(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore,
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3 changes: 1 addition & 2 deletions llvm/lib/Target/X86/X86InstrInfo.cpp
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Expand Up @@ -957,8 +957,7 @@ bool X86InstrInfo::isReallyTriviallyReMaterializable(
void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
Register DestReg, unsigned SubIdx,
const MachineInstr &Orig,
const TargetRegisterInfo &TRI) const {
const MachineInstr &Orig) const {
bool ClobbersEFLAGS = Orig.modifiesRegister(X86::EFLAGS, &TRI);
if (ClobbersEFLAGS && MBB.computeRegisterLiveness(&TRI, X86::EFLAGS, I) !=
MachineBasicBlock::LQR_Dead) {
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3 changes: 1 addition & 2 deletions llvm/lib/Target/X86/X86InstrInfo.h
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Expand Up @@ -343,8 +343,7 @@ class X86InstrInfo final : public X86GenInstrInfo {
bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override;
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
Register DestReg, unsigned SubIdx,
const MachineInstr &Orig,
const TargetRegisterInfo &TRI) const override;
const MachineInstr &Orig) const override;

/// Given an operand within a MachineInstr, insert preceding code to put it
/// into the right format for a particular kind of LEA instruction. This may
Expand Down