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SPARC: Use RegClassByHwMode instead of PointerLikeRegClass #158271

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Merged
merged 1 commit into from
Sep 19, 2025
Merged

SPARC: Use RegClassByHwMode instead of PointerLikeRegClass #158271

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8 changes: 0 additions & 8 deletions llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -159,14 +159,6 @@ static DecodeStatus DecodeI64RegsRegisterClass(MCInst &Inst, unsigned RegNo,
return DecodeIntRegsRegisterClass(Inst, RegNo, Address, Decoder);
}

// This is used for the type "ptr_rc", which is either IntRegs or I64Regs
// depending on SparcRegisterInfo::getPointerRegClass.
static DecodeStatus DecodePointerLikeRegClass0(MCInst &Inst, unsigned RegNo,
uint64_t Address,
const MCDisassembler *Decoder) {
return DecodeIntRegsRegisterClass(Inst, RegNo, Address, Decoder);
}

static DecodeStatus DecodeFPRegsRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address,
const MCDisassembler *Decoder) {
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21 changes: 19 additions & 2 deletions llvm/lib/Target/Sparc/SparcInstrInfo.td
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Expand Up @@ -95,10 +95,27 @@ def HasFSMULD : Predicate<"!Subtarget->hasNoFSMULD()">;
// will pick deprecated instructions.
def UseDeprecatedInsts : Predicate<"Subtarget->useV8DeprecatedInsts()">;

//===----------------------------------------------------------------------===//
// HwModes Pattern Stuff
//===----------------------------------------------------------------------===//

defvar SPARC32 = DefaultMode;
def SPARC64 : HwMode<[Is64Bit]>;
Comment on lines +102 to +103
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There isn't a default mode really, so maybe:

Suggested change
defvar SPARC32 = DefaultMode;
def SPARC64 : HwMode<[Is64Bit]>;
def Mode32Bit : HwMode<[Is32Bit]>;
def Mode64Bit : HwMode<[Is64Bit]>;

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Not sure what you mean, there is a default mode. It's also weirdly baked into the tablegen APIs for it too

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I meant default mode in hardware. This is more of a stylistic suggestion.


//===----------------------------------------------------------------------===//
// Instruction Pattern Stuff
//===----------------------------------------------------------------------===//

def sparc_ptr_rc : RegClassByHwMode<
[SPARC32, SPARC64],
[IntRegs, I64Regs]>;

// Both cases can use the same decoder method, so avoid the dispatch
// by hwmode by setting an explicit DecoderMethod
def ptr_op : RegisterOperand<sparc_ptr_rc> {
let DecoderMethod = "DecodeIntRegsRegisterClass";
}

// FIXME these should have AsmOperandClass.
def uimm3 : PatLeaf<(imm), [{ return isUInt<3>(N->getZExtValue()); }]>;

Expand Down Expand Up @@ -178,12 +195,12 @@ def simm13Op : Operand<iPTR> {

def MEMrr : Operand<iPTR> {
let PrintMethod = "printMemOperand";
let MIOperandInfo = (ops ptr_rc, ptr_rc);
let MIOperandInfo = (ops ptr_op, ptr_op);
let ParserMatchClass = SparcMEMrrAsmOperand;
}
def MEMri : Operand<iPTR> {
let PrintMethod = "printMemOperand";
let MIOperandInfo = (ops ptr_rc, simm13Op);
let MIOperandInfo = (ops ptr_op, simm13Op);
let ParserMatchClass = SparcMEMriAsmOperand;
}

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