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[RISCV] Fix illegal build_vector when lowering double id buildvec on RV32 #67017

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Merged
merged 1 commit into from
Oct 4, 2023
+134 −7
Merged

[RISCV] Fix illegal build_vector when lowering double id buildvec on RV32 #67017

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10 changes: 4 additions & 6 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
View file
Original file line number Diff line number Diff line change
@@ -3386,18 +3386,16 @@ static SDValue lowerBuildVectorOfConstants(SDValue Op, SelectionDAG &DAG,
VID = convertFromScalableVector(VIDVT, VID, DAG, Subtarget);
if ((StepOpcode == ISD::MUL && SplatStepVal != 1) ||
(StepOpcode == ISD::SHL && SplatStepVal != 0)) {
SDValue SplatStep = DAG.getSplatBuildVector(
VIDVT, DL, DAG.getConstant(SplatStepVal, DL, XLenVT));
SDValue SplatStep = DAG.getConstant(SplatStepVal, DL, VIDVT);
VID = DAG.getNode(StepOpcode, DL, VIDVT, VID, SplatStep);
}
if (StepDenominator != 1) {
SDValue SplatStep = DAG.getSplatBuildVector(
VIDVT, DL, DAG.getConstant(Log2_64(StepDenominator), DL, XLenVT));
SDValue SplatStep =
DAG.getConstant(Log2_64(StepDenominator), DL, VIDVT);
VID = DAG.getNode(ISD::SRL, DL, VIDVT, VID, SplatStep);
}
if (Addend != 0 || Negate) {
SDValue SplatAddend = DAG.getSplatBuildVector(
VIDVT, DL, DAG.getConstant(Addend, DL, XLenVT));
SDValue SplatAddend = DAG.getConstant(Addend, DL, VIDVT);
VID = DAG.getNode(Negate ? ISD::SUB : ISD::ADD, DL, VIDVT, SplatAddend,
VID);
}
129 changes: 129 additions & 0 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
View file
Original file line number Diff line number Diff line change
@@ -1083,3 +1083,132 @@ define <2 x float> @signbits() {
entry:
ret <2 x float> <float 0x36A0000000000000, float 0.000000e+00>
}

define <2 x half> @vid_v2f16() {
; CHECK-LABEL: vid_v2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: vfcvt.f.x.v v8, v8
; CHECK-NEXT: ret
ret <2 x half> <half 0.0, half 1.0>
}

define <2 x half> @vid_addend1_v2f16() {
; CHECK-LABEL: vid_addend1_v2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: vadd.vi v8, v8, 1
; CHECK-NEXT: vfcvt.f.x.v v8, v8
; CHECK-NEXT: ret
ret <2 x half> <half 1.0, half 2.0>
}

define <2 x half> @vid_denominator2_v2f16() {
; CHECK-LABEL: vid_denominator2_v2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI27_0)
; CHECK-NEXT: addi a0, a0, %lo(.LCPI27_0)
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: ret
ret <2 x half> <half 0.5, half 1.0>
}

define <2 x half> @vid_step2_v2f16() {
; CHECK-LABEL: vid_step2_v2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: vadd.vv v8, v8, v8
; CHECK-NEXT: vfcvt.f.x.v v8, v8
; CHECK-NEXT: ret
ret <2 x half> <half 0.0, half 2.0>
}

define <2 x float> @vid_v2f32() {
; CHECK-LABEL: vid_v2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: vfcvt.f.x.v v8, v8
; CHECK-NEXT: ret
ret <2 x float> <float 0.0, float 1.0>
}

define <2 x float> @vid_addend1_v2f32() {
; CHECK-LABEL: vid_addend1_v2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: vadd.vi v8, v8, 1
; CHECK-NEXT: vfcvt.f.x.v v8, v8
; CHECK-NEXT: ret
ret <2 x float> <float 1.0, float 2.0>
}

define <2 x float> @vid_denominator2_v2f32() {
; CHECK-LABEL: vid_denominator2_v2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI31_0)
; CHECK-NEXT: addi a0, a0, %lo(.LCPI31_0)
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: ret
ret <2 x float> <float 0.5, float 1.0>
}

define <2 x float> @vid_step2_v2f32() {
; CHECK-LABEL: vid_step2_v2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: vadd.vv v8, v8, v8
; CHECK-NEXT: vfcvt.f.x.v v8, v8
; CHECK-NEXT: ret
ret <2 x float> <float 0.0, float 2.0>
}

define <2 x double> @vid_v2f64() {
; CHECK-LABEL: vid_v2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: vfcvt.f.x.v v8, v8
; CHECK-NEXT: ret
ret <2 x double> <double 0.0, double 1.0>
}

define <2 x double> @vid_addend1_v2f64() {
; CHECK-LABEL: vid_addend1_v2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: vadd.vi v8, v8, 1
; CHECK-NEXT: vfcvt.f.x.v v8, v8
; CHECK-NEXT: ret
ret <2 x double> <double 1.0, double 2.0>
}

define <2 x double> @vid_denominator2_v2f64() {
; CHECK-LABEL: vid_denominator2_v2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI35_0)
; CHECK-NEXT: addi a0, a0, %lo(.LCPI35_0)
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: ret
ret <2 x double> <double 0.5, double 1.0>
}

define <2 x double> @vid_step2_v2f64() {
; CHECK-LABEL: vid_step2_v2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: vadd.vv v8, v8, v8
; CHECK-NEXT: vfcvt.f.x.v v8, v8
; CHECK-NEXT: ret
ret <2 x double> <double 0.0, double 2.0>
}
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
View file
Original file line number Diff line number Diff line change
@@ -259,7 +259,7 @@ define <4 x i8> @buildvec_vid_stepn3_add3_v4i8() {
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vmv.v.i v9, 3
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: li a0, -3
; CHECK-NEXT: li a0, 253
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This and the regressions below are caused by SelectionDAG::getConstant not sign-extending the splat value. I'll try to fix this in a separate PR

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#67027 should fix this

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@lukel97 lukel97 Sep 27, 2023 •
edited
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After rebasing on top of #67419 it looks like it didn't catch this one, but #67027 should still fix it

This still remains: #67027 only sign extends if we're trying to extend an i32 to i64 on RV64

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Talked to Luke about this offline. My summary is that while we are generating the zero vs sign extended constant for the i8, that we believe hasAllNBitUsers handles this case. Our theory is that the difference in the LI immediate comes down to the fact that using a different constant on the LI isn't profitable (in either direction) - i.e. no rooting transform. This seems backed up by the fact we don't see any other test differences which are material.

; CHECK-NEXT: vmadd.vx v8, a0, v9
; CHECK-NEXT: ret
ret <4 x i8> <i8 3, i8 0, i8 -3, i8 -6>