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70de0e ([VP][RISCV] Add vp.fshl/fshr and RISC-V support.) introduced VP_FSHL and VP_FSHR, by using a generic expansion for all targets: the core of this change is in TargetLowering. However, the commit erroneously introduced dead code in RISCVISelLowering. Remove this dead code.

70de0e ([VP][RISCV] Add vp.fshl/fshr and RISC-V support.) introduced
VP_FSHL and VP_FSHR, by using a generic expansion for all targets: the
core of this change is in TargetLowering. However, the commit
erroneously introduced dead code in RISCVISelLowering. Remove this dead
code.
@llvmbot
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llvmbot commented Sep 21, 2023

@llvm/pr-subscribers-llvm-selectiondag

@llvm/pr-subscribers-backend-risc-v

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70de0e ([VP][RISCV] Add vp.fshl/fshr and RISC-V support.) introduced VP_FSHL and VP_FSHR, by using a generic expansion for all targets: the core of this change is in TargetLowering. However, the commit erroneously introduced dead code in RISCVISelLowering. Remove this dead code.


Full diff: https://github.com/llvm/llvm-project/pull/67035.diff

1 Files Affected:

  • (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (-2)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index f1cea6c6756f4fc..9533f746305c3ae 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -715,8 +715,6 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
       setOperationAction({ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}, VT,
                          Legal);
 
-      setOperationAction({ISD::VP_FSHL, ISD::VP_FSHR}, VT, Expand);
-
       // Custom-lower extensions and truncations from/to mask types.
       setOperationAction({ISD::ANY_EXTEND, ISD::SIGN_EXTEND, ISD::ZERO_EXTEND},
                          VT, Custom);

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LGTM

@artagnon artagnon merged commit 3b3ff5c into llvm:main Sep 21, 2023
@artagnon artagnon deleted the riscv-isel-nfc branch September 21, 2023 17:18
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3 participants