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[AArch64][SME] Remove immediate argument restriction for svldr and svstr #68908

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Merged
merged 7 commits into from
Oct 17, 2023
Merged

[AArch64][SME] Remove immediate argument restriction for svldr and svstr #68908

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000c993
[AArch64][SME] Remove immediate argument restriction for svldr and svstr
SamTebbs33 Oct 6, 2023
cbbb4e2
fixup! inline EmitTileslice
SamTebbs33 Oct 17, 2023
50e226a
fixup! format
SamTebbs33 Oct 17, 2023
b29f6d5
fixup! remove unnecessary 32 bit cast and reorder operands
SamTebbs33 Oct 17, 2023
48c4b39
fixup! remove unnecessary constantint cast
SamTebbs33 Oct 17, 2023
a786db5
fixup! make vnum signed in tests
SamTebbs33 Oct 17, 2023
54a1a1d
fixup! remove reference to EmitTileslice
SamTebbs33 Oct 17, 2023
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10 changes: 4 additions & 6 deletions clang/include/clang/Basic/arm_sme.td
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Original file line number Diff line number Diff line change
Expand Up @@ -44,10 +44,9 @@ defm SVLD1_ZA32 : ZALoad<"za32", "i", "aarch64_sme_ld1w", [ImmCheck<0, ImmCheck0
defm SVLD1_ZA64 : ZALoad<"za64", "l", "aarch64_sme_ld1d", [ImmCheck<0, ImmCheck0_7>]>;
defm SVLD1_ZA128 : ZALoad<"za128", "q", "aarch64_sme_ld1q", [ImmCheck<0, ImmCheck0_15>]>;

def SVLDR_VNUM_ZA : MInst<"svldr_vnum_za", "vmQi", "",
def SVLDR_VNUM_ZA : MInst<"svldr_vnum_za", "vmQl", "",
[IsOverloadNone, IsStreamingCompatible, IsSharedZA],
MemEltTyDefault, "aarch64_sme_ldr",
[ImmCheck<2, ImmCheck0_15>]>;
MemEltTyDefault, "aarch64_sme_ldr">;

def SVLDR_ZA : MInst<"svldr_za", "vmQ", "",
[IsOverloadNone, IsStreamingCompatible, IsSharedZA],
Expand Down Expand Up @@ -82,10 +81,9 @@ defm SVST1_ZA32 : ZAStore<"za32", "i", "aarch64_sme_st1w", [ImmCheck<0, ImmCheck
defm SVST1_ZA64 : ZAStore<"za64", "l", "aarch64_sme_st1d", [ImmCheck<0, ImmCheck0_7>]>;
defm SVST1_ZA128 : ZAStore<"za128", "q", "aarch64_sme_st1q", [ImmCheck<0, ImmCheck0_15>]>;

def SVSTR_VNUM_ZA : MInst<"svstr_vnum_za", "vm%i", "",
def SVSTR_VNUM_ZA : MInst<"svstr_vnum_za", "vm%l", "",
[IsOverloadNone, IsStreamingCompatible, IsSharedZA, IsPreservesZA],
MemEltTyDefault, "aarch64_sme_str",
[ImmCheck<2, ImmCheck0_15>]>;
MemEltTyDefault, "aarch64_sme_str">;

def SVSTR_ZA : MInst<"svstr_za", "vm%", "",
[IsOverloadNone, IsStreamingCompatible, IsSharedZA, IsPreservesZA],
Expand Down
15 changes: 5 additions & 10 deletions clang/lib/CodeGen/CGBuiltin.cpp
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Expand Up @@ -9653,11 +9653,6 @@ Value *CodeGenFunction::EmitSVEMaskedStore(const CallExpr *E,
return Store;
}

Value *CodeGenFunction::EmitTileslice(Value *Offset, Value *Base) {
llvm::Value *CastOffset = Builder.CreateIntCast(Offset, Int32Ty, false);
return Builder.CreateAdd(Base, CastOffset, "tileslice");
}

Value *CodeGenFunction::EmitSMELd1St1(const SVETypeFlags &TypeFlags,
SmallVectorImpl<Value *> &Ops,
unsigned IntID) {
Expand Down Expand Up @@ -9716,13 +9711,13 @@ Value *CodeGenFunction::EmitSMELdrStr(const SVETypeFlags &TypeFlags,
if (Ops.size() == 3) {
Function *Cntsb = CGM.getIntrinsic(Intrinsic::aarch64_sme_cntsb);
llvm::Value *CntsbCall = Builder.CreateCall(Cntsb, {}, "svlb");
llvm::Value *MulVL = Builder.CreateMul(
CntsbCall,
Builder.getInt64(cast<llvm::ConstantInt>(Ops[2])->getZExtValue()),
"mulvl");

llvm::Value *VecNum = Ops[2];
llvm::Value *MulVL = Builder.CreateMul(CntsbCall, VecNum, "mulvl");

Ops[1] = Builder.CreateGEP(Int8Ty, Ops[1], MulVL);
Ops[0] = EmitTileslice(Ops[0], Ops[2]);
Ops[0] = Builder.CreateAdd(
Ops[0], Builder.CreateIntCast(VecNum, Int32Ty, true), "tileslice");
Ops.erase(&Ops[2]);
}
Function *F = CGM.getIntrinsic(IntID, {});
Expand Down
1 change: 0 additions & 1 deletion clang/lib/CodeGen/CodeGenFunction.h
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Expand Up @@ -4280,7 +4280,6 @@ class CodeGenFunction : public CodeGenTypeCache {
llvm::Value *EmitSVEMaskedStore(const CallExpr *,
SmallVectorImpl<llvm::Value *> &Ops,
unsigned BuiltinID);
llvm::Value *EmitTileslice(llvm::Value *Offset, llvm::Value *Base);
llvm::Value *EmitSVEPrefetchLoad(const SVETypeFlags &TypeFlags,
SmallVectorImpl<llvm::Value *> &Ops,
unsigned BuiltinID);
Expand Down
16 changes: 16 additions & 0 deletions clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ldr.c
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Expand Up @@ -34,6 +34,22 @@ void test_svldr_vnum_za_1(uint32_t slice_base, const void *ptr) {
// CHECK-NEXT: entry:
// CHECK-NEXT: tail call void @llvm.aarch64.sme.ldr(i32 [[SLICE_BASE:%.*]], ptr [[PTR:%.*]])
// CHECK-NEXT: ret void
//
void test_svldr_za(uint32_t slice_base, const void *ptr) {
svldr_za(slice_base, ptr);
}

// CHECK-C-LABEL: @test_svldr_vnum_za_var(
// CHECK-CXX-LABEL: @_Z22test_svldr_vnum_za_varjPKvl(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[SVLB:%.*]] = tail call i64 @llvm.aarch64.sme.cntsb()
// CHECK-NEXT: [[MULVL:%.*]] = mul i64 [[SVLB]], [[VNUM:%.*]]
// CHECK-NEXT: [[TMP0:%.*]] = getelementptr i8, ptr [[PTR:%.*]], i64 [[MULVL]]
// CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[VNUM:%.*]] to i32
// CHECK-NEXT: [[TILESLICE:%.*]] = add i32 [[TMP1]], [[SLICE_BASE:%.*]]
// CHECK-NEXT: tail call void @llvm.aarch64.sme.ldr(i32 [[TILESLICE]], ptr [[TMP0]])
// CHECK-NEXT: ret void
//
void test_svldr_vnum_za_var(uint32_t slice_base, const void *ptr, int64_t vnum) {
svldr_vnum_za(slice_base, ptr, vnum);
}
15 changes: 15 additions & 0 deletions clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_str.c
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Expand Up @@ -38,3 +38,18 @@ void test_svstr_vnum_za_1(uint32_t slice_base, void *ptr) {
void test_svstr_za(uint32_t slice_base, void *ptr) {
svstr_za(slice_base, ptr);
}

// CHECK-C-LABEL: @test_svstr_vnum_za_var(
// CHECK-CXX-LABEL: @_Z22test_svstr_vnum_za_varjPvl(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[SVLB:%.*]] = tail call i64 @llvm.aarch64.sme.cntsb()
// CHECK-NEXT: [[MULVL:%.*]] = mul i64 [[SVLB]], [[VNUM:%.*]]
// CHECK-NEXT: [[TMP0:%.*]] = getelementptr i8, ptr [[PTR:%.*]], i64 [[MULVL]]
// CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[VNUM:%.*]] to i32
// CHECK-NEXT: [[TILESLICE:%.*]] = add i32 [[TMP1]], [[SLICE_BASE:%.*]]
// CHECK-NEXT: tail call void @llvm.aarch64.sme.str(i32 [[TILESLICE]], ptr [[TMP0]])
// CHECK-NEXT: ret void
//
void test_svstr_vnum_za_var(uint32_t slice_base, void *ptr, int64_t vnum) {
svstr_vnum_za(slice_base, ptr, vnum);
}
8 changes: 0 additions & 8 deletions clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp
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Expand Up @@ -143,11 +143,6 @@ void test_range_0_15(uint32_t slice, svbool_t pg, void *ptr) {
// expected-error@+1 {{argument value 16 is outside the valid range [0, 15]}}
SVE_ACLE_FUNC(svst1_ver_vnum_za128,,,)(16, slice, pg, ptr, 1);

// expected-error@+1 {{argument value 16 is outside the valid range [0, 15]}}
SVE_ACLE_FUNC(svldr_vnum_za,,,)(-1, ptr, 16);
// expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 15]}}
SVE_ACLE_FUNC(svstr_vnum_za,,,)(-1, ptr, -1);

// expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 15]}}
SVE_ACLE_FUNC(svread_hor_za128, _s8, _m,)(svundef_s8(), pg, -1, slice);
// expected-error@+1 {{argument value 16 is outside the valid range [0, 15]}}
Expand All @@ -171,9 +166,6 @@ void test_constant(uint64_t u64, svbool_t pg, void *ptr) {
SVE_ACLE_FUNC(svld1_hor_vnum_za8,,,)(u64, 0, pg, ptr, u64); // expected-error {{argument to 'svld1_hor_vnum_za8' must be a constant integer}}
SVE_ACLE_FUNC(svst1_hor_vnum_za32,,,)(u64, 0, pg, ptr, u64); // expected-error {{argument to 'svst1_hor_vnum_za32' must be a constant integer}}

SVE_ACLE_FUNC(svldr_vnum_za,,,)(u64, ptr, u64); // expected-error {{argument to 'svldr_vnum_za' must be a constant integer}}
SVE_ACLE_FUNC(svstr_vnum_za,,,)(u64, ptr, u64); // expected-error {{argument to 'svstr_vnum_za' must be a constant integer}}

SVE_ACLE_FUNC(svread_ver_za16, _s16, _m,)(svundef_s16(), pg, u64, 0); // expected-error-re {{argument to 'svread_ver_za16{{.*}}_m' must be a constant integer}}
SVE_ACLE_FUNC(svwrite_ver_za64, _s64, _m,)(u64, 0, pg, svundef_s64()); // expected-error-re {{argument to 'svwrite_ver_za64{{.*}}_m' must be a constant integer}}
}