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[X86][MC] Support encoding of EGPR for APX #71909

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Merged
merged 10 commits into from
Nov 13, 2023
Merged

[X86][MC] Support encoding of EGPR for APX #71909

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a18b533
[X86][MC] Support encoding of EGPR for APX
KanRobert Nov 10, 2023
fd41378
format code
KanRobert Nov 10, 2023
37c127e
Format code - remove empty line
KanRobert Nov 10, 2023
cc84e00
Address review comments: assertion, std fallthrough, comments
KanRobert Nov 11, 2023
2f5c834
Revert the change for MRMSrcRegOp4 b/c all its operands are vector re…
KanRobert Nov 11, 2023
4584f30
Add table for EVEX prefix
KanRobert Nov 11, 2023
6ca7cca
Reduce the column of the table in comments
KanRobert Nov 11, 2023
f4830ff
Update comments for SIB
KanRobert Nov 13, 2023
b7c7c53
Address review comments
KanRobert Nov 13, 2023
6faf174
Remove redundant check
KanRobert Nov 13, 2023
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10 changes: 10 additions & 0 deletions llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -106,6 +106,9 @@ class X86AsmParser : public MCTargetAsmParser {

DispEncoding ForcedDispEncoding = DispEncoding_Default;

// Does this instruction use apx extended register?
bool UseApxExtendedReg = false;

private:
SMLoc consumeToken() {
MCAsmParser &Parser = getParser();
Expand Down Expand Up @@ -1410,6 +1413,9 @@ bool X86AsmParser::MatchRegisterByName(MCRegister &RegNo, StringRef RegName,
}
}

if (X86II::isApxExtendedReg(RegNo))
UseApxExtendedReg = true;

// If this is "db[0-15]", match it as an alias
// for dr[0-15].
if (RegNo == 0 && RegName.startswith("db")) {
Expand Down Expand Up @@ -3084,6 +3090,7 @@ bool X86AsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
// Reset the forced VEX encoding.
ForcedVEXEncoding = VEXEncoding_Default;
ForcedDispEncoding = DispEncoding_Default;
UseApxExtendedReg = false;

// Parse pseudo prefixes.
while (true) {
Expand Down Expand Up @@ -3954,6 +3961,9 @@ unsigned X86AsmParser::checkTargetMatchPredicate(MCInst &Inst) {
unsigned Opc = Inst.getOpcode();
const MCInstrDesc &MCID = MII.get(Opc);

if (UseApxExtendedReg && !X86II::canUseApxExtendedReg(MCID))
return Match_Unsupported;

if (ForcedVEXEncoding == VEXEncoding_EVEX &&
(MCID.TSFlags & X86II::EncodingMask) != X86II::EVEX)
return Match_Unsupported;
Expand Down
9 changes: 9 additions & 0 deletions llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
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Original file line number Diff line number Diff line change
Expand Up @@ -1208,6 +1208,12 @@ namespace X86II {
return RegNo >= X86::ZMM0 && RegNo <= X86::ZMM31;
}

/// \returns true if \p RegNo is an apx extended register.
inline bool isApxExtendedReg(unsigned RegNo) {
assert(X86::R31WH - X86::R16 == 95 && "EGPRs are not continuous");
return RegNo >= X86::R16 && RegNo <= X86::R31WH;
}

/// \returns true if the MachineOperand is a x86-64 extended (r8 or
/// higher) register, e.g. r8, xmm8, xmm13, etc.
inline bool isX86_64ExtendedReg(unsigned RegNo) {
Expand All @@ -1218,6 +1224,9 @@ namespace X86II {
(RegNo >= X86::ZMM8 && RegNo <= X86::ZMM31))
return true;

if (isApxExtendedReg(RegNo))
return true;

switch (RegNo) {
default: break;
case X86::R8: case X86::R9: case X86::R10: case X86::R11:
Expand Down
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