[GlobalISel] Lowering of {get,set,reset}_fpenv #75086
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@llvm/pr-subscribers-llvm-globalisel @llvm/pr-subscribers-llvm-support Author: Serge Pavlov (spavloff) ChangesThe intrinsics get_fpenv, set_fpenv and reset_fpenv in this change are implemented as calls to math library functions. Target specific lowering will be implemented later on. Full diff: https://github.com/llvm/llvm-project/pull/75086.diff 10 Files Affected:
diff --git a/llvm/include/llvm/Support/TargetOpcodes.def b/llvm/include/llvm/Support/TargetOpcodes.def
index 3824b1c66951e8..c005218c80f44a 100644
--- a/llvm/include/llvm/Support/TargetOpcodes.def
+++ b/llvm/include/llvm/Support/TargetOpcodes.def
@@ -687,6 +687,9 @@ HANDLE_TARGET_OPCODE(G_FMINIMUM)
HANDLE_TARGET_OPCODE(G_FMAXIMUM)
/// Access to FP environment.
+HANDLE_TARGET_OPCODE(G_GET_FPENV)
+HANDLE_TARGET_OPCODE(G_SET_FPENV)
+HANDLE_TARGET_OPCODE(G_RESET_FPENV)
HANDLE_TARGET_OPCODE(G_GET_FPMODE)
HANDLE_TARGET_OPCODE(G_SET_FPMODE)
HANDLE_TARGET_OPCODE(G_RESET_FPMODE)
diff --git a/llvm/include/llvm/Target/GenericOpcodes.td b/llvm/include/llvm/Target/GenericOpcodes.td
index 73e38b15bf6719..2c73b67f9e1af0 100644
--- a/llvm/include/llvm/Target/GenericOpcodes.td
+++ b/llvm/include/llvm/Target/GenericOpcodes.td
@@ -1020,6 +1020,27 @@ def G_FNEARBYINT : GenericInstruction {
// it is modeled as a side effect, because constrained intrinsics use the same
// method.
+// Reading floating-point environment.
+def G_GET_FPENV : GenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins);
+ let hasSideEffects = true;
+}
+
+// Setting floating-point environment.
+def G_SET_FPENV : GenericInstruction {
+ let OutOperandList = (outs);
+ let InOperandList = (ins type0:$src);
+ let hasSideEffects = true;
+}
+
+// Setting default floating-point environment.
+def G_RESET_FPENV : GenericInstruction {
+ let OutOperandList = (outs);
+ let InOperandList = (ins);
+ let hasSideEffects = true;
+}
+
// Reading floating-point control modes.
def G_GET_FPMODE : GenericInstruction {
let OutOperandList = (outs type0:$dst);
diff --git a/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td b/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
index f28c1edc3d95d8..7bc9ee82841b30 100644
--- a/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
+++ b/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
@@ -116,6 +116,9 @@ def : GINodeEquiv<G_INTRINSIC, intrinsic_wo_chain> {
let IfConvergent = G_INTRINSIC_CONVERGENT;
}
+def : GINodeEquiv<G_GET_FPENV, get_fpenv>;
+def : GINodeEquiv<G_SET_FPENV, set_fpenv>;
+def : GINodeEquiv<G_RESET_FPENV, reset_fpenv>;
def : GINodeEquiv<G_GET_FPMODE, get_fpmode>;
def : GINodeEquiv<G_SET_FPMODE, set_fpmode>;
def : GINodeEquiv<G_RESET_FPMODE, reset_fpmode>;
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index 27a53e55f32fa3..cd9fff35a80ac1 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -1842,6 +1842,8 @@ unsigned IRTranslator::getSimpleIntrinsicOpcode(Intrinsic::ID ID) {
return TargetOpcode::G_LROUND;
case Intrinsic::llround:
return TargetOpcode::G_LLROUND;
+ case Intrinsic::get_fpenv:
+ return TargetOpcode::G_GET_FPENV;
case Intrinsic::get_fpmode:
return TargetOpcode::G_GET_FPMODE;
}
@@ -2425,6 +2427,16 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
return true;
}
+ case Intrinsic::set_fpenv: {
+ Value *FPEnv = CI.getOperand(0);
+ MIRBuilder.buildInstr(TargetOpcode::G_SET_FPENV, {},
+ { getOrCreateVReg(*FPEnv) });
+ return true;
+ }
+ case Intrinsic::reset_fpenv: {
+ MIRBuilder.buildInstr(TargetOpcode::G_RESET_FPENV, {}, {});
+ return true;
+ }
case Intrinsic::set_fpmode: {
Value *FPState = CI.getOperand(0);
MIRBuilder.buildInstr(TargetOpcode::G_SET_FPMODE, {},
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index 37e7153be5720e..d4b3f0c5703a45 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -800,6 +800,13 @@ static RTLIB::Libcall
getStateLibraryFunctionFor(MachineInstr &MI, const TargetLowering &TLI) {
RTLIB::Libcall RTLibcall;
switch (MI.getOpcode()) {
+ case TargetOpcode::G_GET_FPENV:
+ RTLibcall = RTLIB::FEGETENV;
+ break;
+ case TargetOpcode::G_SET_FPENV:
+ case TargetOpcode::G_RESET_FPENV:
+ RTLibcall = RTLIB::FESETENV;
+ break;
case TargetOpcode::G_GET_FPMODE:
RTLibcall = RTLIB::FEGETMODE;
break;
@@ -1031,18 +1038,21 @@ LegalizerHelper::libcall(MachineInstr &MI, LostDebugLocObserver &LocObserver) {
MI.eraseFromParent();
return Result;
}
+ case TargetOpcode::G_GET_FPENV:
case TargetOpcode::G_GET_FPMODE: {
LegalizeResult Result = createGetStateLibcall(MIRBuilder, MI);
if (Result != Legalized)
return Result;
break;
}
+ case TargetOpcode::G_SET_FPENV:
case TargetOpcode::G_SET_FPMODE: {
LegalizeResult Result = createSetStateLibcall(MIRBuilder, MI);
if (Result != Legalized)
return Result;
break;
}
+ case TargetOpcode::G_RESET_FPENV:
case TargetOpcode::G_RESET_FPMODE: {
LegalizeResult Result = createResetStateLibcall(MIRBuilder, MI);
if (Result != Legalized)
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index a35957c34a596b..86e8047a3c0a4d 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -1122,6 +1122,8 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
getActionDefinitionsBuilder(G_FMAD).lower();
// Access to floating-point environment.
+ getActionDefinitionsBuilder({G_GET_FPENV, G_SET_FPENV, G_RESET_FPENV})
+ .libcall();
getActionDefinitionsBuilder({G_GET_FPMODE, G_SET_FPMODE, G_RESET_FPMODE})
.libcall();
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-fpenv.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-fpenv.ll
index fda9269d423d05..9a8e5529f0a1e4 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-fpenv.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-fpenv.ll
@@ -1,10 +1,47 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc -O0 -mtriple=aarch64-linux-gnu -global-isel -stop-after=irtranslator %s -o - | FileCheck %s
+declare i64 @llvm.get.fpenv.i64()
+declare void @llvm.set.fpenv.i64(i64 %fpenv)
+declare void @llvm.reset.fpenv()
declare i32 @llvm.get.fpmode.i32()
declare void @llvm.set.fpmode.i32(i32 %fpmode)
declare void @llvm.reset.fpmode()
+define i64 @func_get_fpenv() #0 {
+ ; CHECK-LABEL: name: func_get_fpenv
+ ; CHECK: bb.1.entry:
+ ; CHECK-NEXT: [[GET_FPENV:%[0-9]+]]:_(s64) = G_GET_FPENV
+ ; CHECK-NEXT: $x0 = COPY [[GET_FPENV]](s64)
+ ; CHECK-NEXT: RET_ReallyLR implicit $x0
+entry:
+ %fpenv = call i64 @llvm.get.fpenv.i64()
+ ret i64 %fpenv
+}
+
+define void @func_set_fpenv(i64 %fpenv) #0 {
+ ; CHECK-LABEL: name: func_set_fpenv
+ ; CHECK: bb.1.entry:
+ ; CHECK-NEXT: liveins: $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
+ ; CHECK-NEXT: G_SET_FPENV [[COPY]](s64)
+ ; CHECK-NEXT: RET_ReallyLR
+entry:
+ call void @llvm.set.fpenv.i64(i64 %fpenv)
+ ret void
+}
+
+define void @func_reset_fpenv() #0 {
+ ; CHECK-LABEL: name: func_reset_fpenv
+ ; CHECK: bb.1.entry:
+ ; CHECK-NEXT: G_RESET_FPENV
+ ; CHECK-NEXT: RET_ReallyLR
+entry:
+ call void @llvm.reset.fpenv()
+ ret void
+}
+
define i32 @func_get_fpmode() #0 {
; CHECK-LABEL: name: func_get_fpmode
; CHECK: bb.1.entry:
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fpenv.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fpenv.mir
new file mode 100644
index 00000000000000..7076e4fbe2edff
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fpenv.mir
@@ -0,0 +1,88 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
+# RUN: llc -mtriple=aarch64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s
+
+--- |
+ target triple = "aarch64-unknown-linux-gnu"
+
+ declare i64 @llvm.get.fpenv.i64()
+ declare void @llvm.set.fpenv.i64(i64)
+ declare void @llvm.reset.fpenv()
+
+ define i64 @func_get_fpenv() {
+ entry:
+ %fpenv = call i64 @llvm.get.fpenv.i64()
+ ret i64 %fpenv
+ }
+
+ define void @func_set_fpenv(i64 %fpenv) {
+ entry:
+ call void @llvm.set.fpenv.i64(i64 %fpenv)
+ ret void
+ }
+
+ define void @func_reset() {
+ entry:
+ call void @llvm.reset.fpenv()
+ ret void
+ }
+
+...
+---
+name: func_get_fpenv
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ ; CHECK-LABEL: name: func_get_fpenv
+ ; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0
+ ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
+ ; CHECK-NEXT: $x0 = COPY [[FRAME_INDEX]](p0)
+ ; CHECK-NEXT: BL &fegetenv, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0
+ ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s64) from %stack.0)
+ ; CHECK-NEXT: $x0 = COPY [[LOAD]](s64)
+ ; CHECK-NEXT: RET_ReallyLR implicit $x0
+ %0:_(s64) = G_GET_FPENV
+ $x0 = COPY %0(s64)
+ RET_ReallyLR implicit $x0
+
+...
+---
+name: func_set_fpenv
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $x0
+
+ ; CHECK-LABEL: name: func_set_fpenv
+ ; CHECK: liveins: $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
+ ; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0
+ ; CHECK-NEXT: G_STORE [[COPY]](s64), [[FRAME_INDEX]](p0) :: (store (s64) into %stack.0)
+ ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
+ ; CHECK-NEXT: $x0 = COPY [[FRAME_INDEX]](p0)
+ ; CHECK-NEXT: BL &fesetenv, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0
+ ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; CHECK-NEXT: RET_ReallyLR
+ %0:_(s64) = COPY $x0
+ G_SET_FPENV %0(s64)
+ RET_ReallyLR
+
+...
+---
+name: func_reset
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ ; CHECK-LABEL: name: func_reset
+ ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[C]](s64)
+ ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
+ ; CHECK-NEXT: $x0 = COPY [[INTTOPTR]](p0)
+ ; CHECK-NEXT: BL &fesetenv, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0
+ ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; CHECK-NEXT: RET_ReallyLR
+ G_RESET_FPENV
+ RET_ReallyLR
+
+...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
index 178db852e35b7e..fc519dbf1c4b1c 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
@@ -554,6 +554,17 @@
# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
+# DEBUG-NEXT: G_GET_FPENV (opcode 196): 1 type index, 0 imm indices
+# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
+# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
+# DEBUG-NEXT: G_SET_FPENV (opcode 197): 1 type index, 0 imm indices
+# DEBUG-NEXT: .. opcode 197 is aliased to 196
+# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
+# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
+# DEBUG-NEXT: G_RESET_FPENV (opcode 198): 0 type indices, 0 imm indices
+# DEBUG-NEXT: .. opcode 198 is aliased to 196
+# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
+# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: G_GET_FPMODE (opcode {{[0-9]+}}): 1 type index, 0 imm indices
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
diff --git a/llvm/test/CodeGen/AArch64/fpenv.ll b/llvm/test/CodeGen/AArch64/fpenv.ll
index 3a307f7731037a..cd1d9499b0d7ac 100644
--- a/llvm/test/CodeGen/AArch64/fpenv.ll
+++ b/llvm/test/CodeGen/AArch64/fpenv.ll
@@ -62,4 +62,47 @@ define void @func_set_rounding_downward() {
ret void
}
+define i64 @get_fpenv_01() nounwind {
+; CHECK-LABEL: get_fpenv_01:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT: add x0, sp, #8
+; CHECK-NEXT: bl fegetenv
+; CHECK-NEXT: ldr x0, [sp, #8]
+; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: ret
+entry:
+ %fpenv = call i64 @llvm.get.fpenv.i64()
+ ret i64 %fpenv
+}
+
+define void @set_fpenv_01(i64 %fpenv) nounwind {
+; CHECK-LABEL: set_fpenv_01:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: stp x30, x0, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT: add x0, sp, #8
+; CHECK-NEXT: bl fesetenv
+; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: ret
+entry:
+ call void @llvm.set.fpenv.i64(i64 %fpenv)
+ ret void
+}
+
+define void @reset_fpenv_01() nounwind {
+; CHECK-LABEL: reset_fpenv_01:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT: mov x0, #-1 // =0xffffffffffffffff
+; CHECK-NEXT: bl fesetenv
+; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: ret
+entry:
+ call void @llvm.reset.fpenv()
+ ret void
+}
+
declare void @llvm.set.rounding(i32)
+declare i64 @llvm.get.fpenv.i64()
+declare void @llvm.set.fpenv.i64(i64 %fpenv)
+declare void @llvm.reset.fpenv()
|
|
✅ With the latest revision this PR passed the C/C++ code formatter. |
tschuett
reviewed
Dec 11, 2023
| @@ -1122,6 +1122,8 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) | |||
| getActionDefinitionsBuilder(G_FMAD).lower(); | |||
|
|
|||
| // Access to floating-point environment. | |||
| getActionDefinitionsBuilder({G_GET_FPENV, G_SET_FPENV, G_RESET_FPENV}) | |||
There was a problem hiding this comment.
You could merge them into one builder. They have similar concepts and similar legalization strategies.
tschuett
reviewed
Dec 12, 2023
llvm/test/CodeGen/AArch64/fpenv.ll
Outdated
| @@ -62,4 +62,47 @@ define void @func_set_rounding_downward() { | |||
| ret void | |||
| } | |||
|
|
|||
| define i64 @get_fpenv_01() nounwind { | |||
There was a problem hiding this comment.
This is presumably not testing what you planned. The RUN line does not contain the string globalisel. It is testing DAG code generation. If you look at the sister file xtn.ll, it has two RUN lines to test code generation for both selectors and highlight their differences.
aemerson
approved these changes
Jan 3, 2024
arsenm
reviewed
Jan 4, 2024
| declare void @llvm.set.fpenv.i64(i64) | ||
| declare void @llvm.reset.fpenv() | ||
|
|
||
| define i64 @func_get_fpenv() { |
| name: func_get_fpenv | ||
| tracksRegLiveness: true | ||
| body: | | ||
| bb.1.entry: |
The intrinsics get_fpenv, set_fpenv and reset_fpenv in this change are implemented as calls to math library functions. Target specific lowering will be implemented later on.
- fix clang-format errors, - merge builders for FP environment.
- Tests for *_fpenv intrinsics are moved to a separate file in the directory AArch64/GlobalISel. - Update the test TableGen/GlobalISelEmitter.td
Call to fesetenv is now tail-optimized.
arsenm
approved these changes
Jan 9, 2024
justinfargnoli
pushed a commit
to justinfargnoli/llvm-project
that referenced
this pull request
Jan 28, 2024
The intrinsics get_fpenv, set_fpenv and reset_fpenv in this change are implemented as calls to math library functions. Target specific lowering will be implemented later on.
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The intrinsics get_fpenv, set_fpenv and reset_fpenv in this change are implemented as calls to math library functions. Target specific lowering will be implemented later on.