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[X86][MC] Support Enc/Dec for EGPR for promoted AMX-TILE instruction #76210

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Merged
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Dec 26, 2023
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[X86][MC] Support Enc/Dec for EGPR for promoted AMX-TILE instruction #76210

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[X86][MC] Support Enc/Dec for EGPR for promoted AMX-TILE instruction
XinWang10 Dec 22, 2023
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XinWang10 Dec 25, 2023
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XinWang10 Dec 25, 2023
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XinWang10 Dec 25, 2023
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68 changes: 39 additions & 29 deletions llvm/lib/Target/X86/X86InstrAMX.td
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Original file line number Diff line number Diff line change
Expand Up @@ -14,35 +14,45 @@
//===----------------------------------------------------------------------===//
// AMX instructions

let Predicates = [HasAMXTILE, In64BitMode] in {
let SchedRW = [WriteSystem] in {
let hasSideEffects = 1,
Defs = [TMM0,TMM1,TMM2,TMM3,TMM4,TMM5,TMM6,TMM7] in
def LDTILECFG : I <0x49, MRM0m, (outs), (ins opaquemem:$src),
"ldtilecfg\t$src",
[(int_x86_ldtilecfg addr:$src)]>, VEX, T8;
let hasSideEffects = 1 in
def STTILECFG : I <0x49, MRM0m, (outs), (ins opaquemem:$src),
"sttilecfg\t$src",
[(int_x86_sttilecfg addr:$src)]>, VEX, T8, PD;
let mayLoad = 1 in
def TILELOADD : I<0x4b, MRMSrcMemFSIB, (outs TILE:$dst),
(ins sibmem:$src),
"tileloadd\t{$src, $dst|$dst, $src}", []>,
VEX, T8, XD;
let mayLoad = 1 in
def TILELOADDT1 : I<0x4b, MRMSrcMemFSIB, (outs TILE:$dst),
(ins sibmem:$src),
"tileloaddt1\t{$src, $dst|$dst, $src}", []>,
VEX, T8, PD;
multiclass AMX_TILE_COMMON<string Suffix, Predicate HasEGPR> {
let Predicates = [HasAMXTILE, HasEGPR, In64BitMode] in {
let hasSideEffects = 1,
Defs = [TMM0,TMM1,TMM2,TMM3,TMM4,TMM5,TMM6,TMM7] in
def LDTILECFG#Suffix : I<0x49, MRM0m, (outs), (ins opaquemem:$src),
"ldtilecfg\t$src",
[(int_x86_ldtilecfg addr:$src)]>,
T8, PS;
let hasSideEffects = 1 in
def STTILECFG#Suffix : I<0x49, MRM0m, (outs), (ins opaquemem:$src),
"sttilecfg\t$src",
[(int_x86_sttilecfg addr:$src)]>,
T8, PD;
let mayLoad = 1 in
def TILELOADD#Suffix : I<0x4b, MRMSrcMemFSIB, (outs TILE:$dst),
(ins sibmem:$src),
"tileloadd\t{$src, $dst|$dst, $src}", []>,
T8, XD;
let mayLoad = 1 in
def TILELOADDT1#Suffix : I<0x4b, MRMSrcMemFSIB, (outs TILE:$dst),
(ins sibmem:$src),
"tileloaddt1\t{$src, $dst|$dst, $src}", []>,
T8, PD;
let mayStore = 1 in
def TILESTORED#Suffix : I<0x4b, MRMDestMemFSIB, (outs),
(ins sibmem:$dst, TILE:$src),
"tilestored\t{$src, $dst|$dst, $src}", []>,
T8, XS;
}
}

let SchedRW = [WriteSystem] in {
defm "" : AMX_TILE_COMMON<"", NoEGPR>, VEX;
defm "" : AMX_TILE_COMMON<"_EVEX", HasEGPR>, EVEX, NoCD8;

let Predicates = [HasAMXTILE, In64BitMode] in {
let Defs = [TMM0,TMM1,TMM2,TMM3,TMM4,TMM5,TMM6,TMM7] in
def TILERELEASE : I<0x49, MRM_C0, (outs), (ins),
"tilerelease", [(int_x86_tilerelease)]>, VEX, T8;
let mayStore = 1 in
def TILESTORED : I<0x4b, MRMDestMemFSIB, (outs),
(ins sibmem:$dst, TILE:$src),
"tilestored\t{$src, $dst|$dst, $src}", []>,
VEX, T8, XS;
"tilerelease", [(int_x86_tilerelease)]>, VEX, T8, PS;
def TILEZERO : I<0x49, MRMr0, (outs TILE:$dst), (ins),
"tilezero\t$dst", []>,
VEX, T8, XD;
Expand Down Expand Up @@ -82,8 +92,8 @@ let Predicates = [HasAMXTILE, In64BitMode] in {
def PTILEZERO : PseudoI<(outs), (ins u8imm:$src),
[(int_x86_tilezero timm:$src)]>;
}
} // SchedRW
} // HasAMXTILE
} // Predicates
} // SchedRW

let Predicates = [HasAMXINT8, In64BitMode] in {
let SchedRW = [WriteSystem] in {
Expand Down
22 changes: 22 additions & 0 deletions llvm/test/MC/Disassembler/X86/apx/amx-tile.txt
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@@ -0,0 +1,22 @@
# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL

# ATT: ldtilecfg 291(%r28,%r29,4)
# INTEL: ldtilecfg [r28 + 4*r29 + 291]
0x62,0x9a,0x78,0x08,0x49,0x84,0xac,0x23,0x01,0x00,0x00

# ATT: sttilecfg 291(%r28,%r29,4)
# INTEL: sttilecfg [r28 + 4*r29 + 291]
0x62,0x9a,0x79,0x08,0x49,0x84,0xac,0x23,0x01,0x00,0x00

# ATT: tileloadd 291(%r28,%r29,4), %tmm6
# INTEL: tileloadd tmm6, [r28 + 4*r29 + 291]
0x62,0x9a,0x7b,0x08,0x4b,0xb4,0xac,0x23,0x01,0x00,0x00

# ATT: tileloaddt1 291(%r28,%r29,4), %tmm6
# INTEL: tileloaddt1 tmm6, [r28 + 4*r29 + 291]
0x62,0x9a,0x79,0x08,0x4b,0xb4,0xac,0x23,0x01,0x00,0x00

# ATT: tilestored %tmm6, 291(%r28,%r29,4)
# INTEL: tilestored [r28 + 4*r29 + 291], tmm6
0x62,0x9a,0x7a,0x08,0x4b,0xb4,0xac,0x23,0x01,0x00,0x00
24 changes: 24 additions & 0 deletions llvm/test/MC/X86/apx/amx-tile-att.s
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Original file line number Diff line number Diff line change
@@ -0,0 +1,24 @@
# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
# RUN: not llvm-mc -triple i386 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR

# ERROR-COUNT-5: error:
# ERROR-NOT: error:
# CHECK: ldtilecfg 291(%r28,%r29,4)
# CHECK: encoding: [0x62,0x9a,0x78,0x08,0x49,0x84,0xac,0x23,0x01,0x00,0x00]
ldtilecfg 291(%r28,%r29,4)

# CHECK: sttilecfg 291(%r28,%r29,4)
# CHECK: encoding: [0x62,0x9a,0x79,0x08,0x49,0x84,0xac,0x23,0x01,0x00,0x00]
sttilecfg 291(%r28,%r29,4)

# CHECK: tileloadd 291(%r28,%r29,4), %tmm6
# CHECK: encoding: [0x62,0x9a,0x7b,0x08,0x4b,0xb4,0xac,0x23,0x01,0x00,0x00]
tileloadd 291(%r28,%r29,4), %tmm6

# CHECK: tileloaddt1 291(%r28,%r29,4), %tmm6
# CHECK: encoding: [0x62,0x9a,0x79,0x08,0x4b,0xb4,0xac,0x23,0x01,0x00,0x00]
tileloaddt1 291(%r28,%r29,4), %tmm6

# CHECK: tilestored %tmm6, 291(%r28,%r29,4)
# CHECK: encoding: [0x62,0x9a,0x7a,0x08,0x4b,0xb4,0xac,0x23,0x01,0x00,0x00]
tilestored %tmm6, 291(%r28,%r29,4)
21 changes: 21 additions & 0 deletions llvm/test/MC/X86/apx/amx-tile-intel.s
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Original file line number Diff line number Diff line change
@@ -0,0 +1,21 @@
# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s

# CHECK: ldtilecfg [r28 + 4*r29 + 291]
# CHECK: encoding: [0x62,0x9a,0x78,0x08,0x49,0x84,0xac,0x23,0x01,0x00,0x00]
ldtilecfg [r28 + 4*r29 + 291]

# CHECK: sttilecfg [r28 + 4*r29 + 291]
# CHECK: encoding: [0x62,0x9a,0x79,0x08,0x49,0x84,0xac,0x23,0x01,0x00,0x00]
sttilecfg [r28 + 4*r29 + 291]

# CHECK: tileloadd tmm6, [r28 + 4*r29 + 291]
# CHECK: encoding: [0x62,0x9a,0x7b,0x08,0x4b,0xb4,0xac,0x23,0x01,0x00,0x00]
tileloadd tmm6, [r28 + 4*r29 + 291]

# CHECK: tileloaddt1 tmm6, [r28 + 4*r29 + 291]
# CHECK: encoding: [0x62,0x9a,0x79,0x08,0x4b,0xb4,0xac,0x23,0x01,0x00,0x00]
tileloaddt1 tmm6, [r28 + 4*r29 + 291]

# CHECK: tilestored [r28 + 4*r29 + 291], tmm6
# CHECK: encoding: [0x62,0x9a,0x7a,0x08,0x4b,0xb4,0xac,0x23,0x01,0x00,0x00]
tilestored [r28 + 4*r29 + 291], tmm6