[NFC][X86] Reorg MC tests for APX promoted instrs #76697
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@llvm/pr-subscribers-backend-x86 @llvm/pr-subscribers-mc Author: None (XinWang10) ChangesAs suggested in #76210, this patch re-organize the mc tests for apx promoted instrs, instr tests within same cpuid would be listed in one test. Patch is 90.63 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/76697.diff 73 Files Affected:
diff --git a/llvm/lib/Target/X86/X86InstrMisc.td b/llvm/lib/Target/X86/X86InstrMisc.td
index 305bd74f7bd70a..67c38bfc7ba41e 100644
--- a/llvm/lib/Target/X86/X86InstrMisc.td
+++ b/llvm/lib/Target/X86/X86InstrMisc.td
@@ -1371,11 +1371,11 @@ multiclass bmi_pdep_pext<string mnemonic, RegisterClass RC,
def rr#Suffix : I<0xF5, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
!strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
[(set RC:$dst, (OpNode RC:$src1, RC:$src2))]>,
- VEX, VVVV, Sched<[WriteALU]>;
+ VEX, NoCD8, VVVV, Sched<[WriteALU]>;
def rm#Suffix : I<0xF5, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
!strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
[(set RC:$dst, (OpNode RC:$src1, (ld_frag addr:$src2)))]>,
- VEX, VVVV, Sched<[WriteALU.Folded, WriteALU.ReadAfterFold]>;
+ VEX, NoCD8, VVVV, Sched<[WriteALU.Folded, WriteALU.ReadAfterFold]>;
}
let Predicates = [HasBMI2, NoEGPR] in {
diff --git a/llvm/lib/Target/X86/X86InstrShiftRotate.td b/llvm/lib/Target/X86/X86InstrShiftRotate.td
index d13e3b7af69a95..f951894db1890c 100644
--- a/llvm/lib/Target/X86/X86InstrShiftRotate.td
+++ b/llvm/lib/Target/X86/X86InstrShiftRotate.td
@@ -868,7 +868,7 @@ let Predicates = [HasBMI2, NoEGPR] in {
defm SHLX64 : bmi_shift<"shlx{q}", GR64, i64mem>, T8, PD, REX_W;
}
-let Predicates = [HasBMI2, HasEGPR] in {
+let Predicates = [HasBMI2, HasEGPR, In64BitMode] in {
defm RORX32 : bmi_rotate<"rorx{l}", GR32, i32mem, "_EVEX">, EVEX;
defm RORX64 : bmi_rotate<"rorx{q}", GR64, i64mem, "_EVEX">, REX_W, EVEX;
defm SARX32 : bmi_shift<"sarx{l}", GR32, i32mem, "_EVEX">, T8, XS, EVEX;
diff --git a/llvm/test/MC/Disassembler/X86/apx/bmi2.txt b/llvm/test/MC/Disassembler/X86/apx/bmi2.txt
new file mode 100644
index 00000000000000..6c39ae2e67005f
--- /dev/null
+++ b/llvm/test/MC/Disassembler/X86/apx/bmi2.txt
@@ -0,0 +1,226 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT: mulxl %ecx, %edx, %r10d
+# INTEL: mulx r10d, edx, ecx
+0x62,0x72,0x6f,0x08,0xf6,0xd1
+
+# ATT: mulxq %r9, %r15, %r11
+# INTEL: mulx r11, r15, r9
+0x62,0x52,0x87,0x08,0xf6,0xd9
+
+# ATT: mulxl 123(%rax,%rbx,4), %ecx, %edx
+# INTEL: mulx edx, ecx, dword ptr [rax + 4*rbx + 123]
+0x62,0xf2,0x77,0x08,0xf6,0x94,0x98,0x7b,0x00,0x00,0x00
+
+# ATT: mulxq 123(%rax,%rbx,4), %r9, %r15
+# INTEL: mulx r15, r9, qword ptr [rax + 4*rbx + 123]
+0x62,0x72,0xb7,0x08,0xf6,0xbc,0x98,0x7b,0x00,0x00,0x00
+
+# ATT: mulxl %r18d, %r22d, %r26d
+# INTEL: mulx r26d, r22d, r18d
+0x62,0x6a,0x4f,0x00,0xf6,0xd2
+
+# ATT: mulxq %r19, %r23, %r27
+# INTEL: mulx r27, r23, r19
+0x62,0x6a,0xc7,0x00,0xf6,0xdb
+
+# ATT: mulxl 291(%r28,%r29,4), %r18d, %r22d
+# INTEL: mulx r22d, r18d, dword ptr [r28 + 4*r29 + 291]
+0x62,0x8a,0x6b,0x00,0xf6,0xb4,0xac,0x23,0x01,0x00,0x00
+
+# ATT: mulxq 291(%r28,%r29,4), %r19, %r23
+# INTEL: mulx r23, r19, qword ptr [r28 + 4*r29 + 291]
+0x62,0x8a,0xe3,0x00,0xf6,0xbc,0xac,0x23,0x01,0x00,0x00
+
+# ATT: pdepl %ecx, %edx, %r10d
+# INTEL: pdep r10d, edx, ecx
+0x62,0x72,0x6f,0x08,0xf5,0xd1
+
+# ATT: pdepq %r9, %r15, %r11
+# INTEL: pdep r11, r15, r9
+0x62,0x52,0x87,0x08,0xf5,0xd9
+
+# ATT: pdepl 123(%rax,%rbx,4), %ecx, %edx
+# INTEL: pdep edx, ecx, dword ptr [rax + 4*rbx + 123]
+0x62,0xf2,0x77,0x08,0xf5,0x54,0x98,0x7b
+
+# ATT: pdepq 123(%rax,%rbx,4), %r9, %r15
+# INTEL: pdep r15, r9, qword ptr [rax + 4*rbx + 123]
+0x62,0x72,0xb7,0x08,0xf5,0x7c,0x98,0x7b
+
+# ATT: pdepl %r18d, %r22d, %r26d
+# INTEL: pdep r26d, r22d, r18d
+0x62,0x6a,0x4f,0x00,0xf5,0xd2
+
+# ATT: pdepq %r19, %r23, %r27
+# INTEL: pdep r27, r23, r19
+0x62,0x6a,0xc7,0x00,0xf5,0xdb
+
+# ATT: pdepl 291(%r28,%r29,4), %r18d, %r22d
+# INTEL: pdep r22d, r18d, dword ptr [r28 + 4*r29 + 291]
+0x62,0x8a,0x6b,0x00,0xf5,0xb4,0xac,0x23,0x01,0x00,0x00
+
+# ATT: pdepq 291(%r28,%r29,4), %r19, %r23
+# INTEL: pdep r23, r19, qword ptr [r28 + 4*r29 + 291]
+0x62,0x8a,0xe3,0x00,0xf5,0xbc,0xac,0x23,0x01,0x00,0x00
+
+# ATT: pextl %ecx, %edx, %r10d
+# INTEL: pext r10d, edx, ecx
+0x62,0x72,0x6e,0x08,0xf5,0xd1
+
+# ATT: pextq %r9, %r15, %r11
+# INTEL: pext r11, r15, r9
+0x62,0x52,0x86,0x08,0xf5,0xd9
+
+# ATT: pextl 123(%rax,%rbx,4), %ecx, %edx
+# INTEL: pext edx, ecx, dword ptr [rax + 4*rbx + 123]
+0x62,0xf2,0x76,0x08,0xf5,0x54,0x98,0x7b
+
+# ATT: pextq 123(%rax,%rbx,4), %r9, %r15
+# INTEL: pext r15, r9, qword ptr [rax + 4*rbx + 123]
+0x62,0x72,0xb6,0x08,0xf5,0x7c,0x98,0x7b
+
+# ATT: pextl %r18d, %r22d, %r26d
+# INTEL: pext r26d, r22d, r18d
+0x62,0x6a,0x4e,0x00,0xf5,0xd2
+
+# ATT: pextq %r19, %r23, %r27
+# INTEL: pext r27, r23, r19
+0x62,0x6a,0xc6,0x00,0xf5,0xdb
+
+# ATT: pextl 291(%r28,%r29,4), %r18d, %r22d
+# INTEL: pext r22d, r18d, dword ptr [r28 + 4*r29 + 291]
+0x62,0x8a,0x6a,0x00,0xf5,0xb4,0xac,0x23,0x01,0x00,0x00
+
+# ATT: pextq 291(%r28,%r29,4), %r19, %r23
+# INTEL: pext r23, r19, qword ptr [r28 + 4*r29 + 291]
+0x62,0x8a,0xe2,0x00,0xf5,0xbc,0xac,0x23,0x01,0x00,0x00
+
+# ATT: rorxl $123, %ecx, %edx
+# INTEL: rorx edx, ecx, 123
+0x62,0xf3,0x7f,0x08,0xf0,0xd1,0x7b
+
+# ATT: rorxq $123, %r9, %r15
+# INTEL: rorx r15, r9, 123
+0x62,0x53,0xff,0x08,0xf0,0xf9,0x7b
+
+# ATT: rorxl $123, 123(%rax,%rbx,4), %ecx
+# INTEL: rorx ecx, dword ptr [rax + 4*rbx + 123], 123
+0x62,0xf3,0x7f,0x08,0xf0,0x8c,0x98,0x7b,0x00,0x00,0x00,0x7b
+
+# ATT: rorxq $123, 123(%rax,%rbx,4), %r9
+# INTEL: rorx r9, qword ptr [rax + 4*rbx + 123], 123
+0x62,0x73,0xff,0x08,0xf0,0x8c,0x98,0x7b,0x00,0x00,0x00,0x7b
+
+# ATT: rorxl $123, %r18d, %r22d
+# INTEL: rorx r22d, r18d, 123
+0x62,0xeb,0x7f,0x08,0xf0,0xf2,0x7b
+
+# ATT: rorxq $123, %r19, %r23
+# INTEL: rorx r23, r19, 123
+0x62,0xeb,0xff,0x08,0xf0,0xfb,0x7b
+
+# ATT: rorxl $123, 291(%r28,%r29,4), %r18d
+# INTEL: rorx r18d, dword ptr [r28 + 4*r29 + 291], 123
+0x62,0x8b,0x7b,0x08,0xf0,0x94,0xac,0x23,0x01,0x00,0x00,0x7b
+
+# ATT: rorxq $123, 291(%r28,%r29,4), %r19
+# INTEL: rorx r19, qword ptr [r28 + 4*r29 + 291], 123
+0x62,0x8b,0xfb,0x08,0xf0,0x9c,0xac,0x23,0x01,0x00,0x00,0x7b
+
+# ATT: sarxl %ecx, %edx, %r10d
+# INTEL: sarx r10d, edx, ecx
+0x62,0x72,0x76,0x08,0xf7,0xd2
+
+# ATT: sarxl %ecx, 123(%rax,%rbx,4), %edx
+# INTEL: sarx edx, dword ptr [rax + 4*rbx + 123], ecx
+0x62,0xf2,0x76,0x08,0xf7,0x94,0x98,0x7b,0x00,0x00,0x00
+
+# ATT: sarxq %r9, %r15, %r11
+# INTEL: sarx r11, r15, r9
+0x62,0x52,0xb6,0x08,0xf7,0xdf
+
+# ATT: sarxq %r9, 123(%rax,%rbx,4), %r15
+# INTEL: sarx r15, qword ptr [rax + 4*rbx + 123], r9
+0x62,0x72,0xb6,0x08,0xf7,0xbc,0x98,0x7b,0x00,0x00,0x00
+
+# ATT: sarxl %r18d, %r22d, %r26d
+# INTEL: sarx r26d, r22d, r18d
+0x62,0x6a,0x6e,0x00,0xf7,0xd6
+
+# ATT: sarxl %r18d, 291(%r28,%r29,4), %r22d
+# INTEL: sarx r22d, dword ptr [r28 + 4*r29 + 291], r18d
+0x62,0x8a,0x6a,0x00,0xf7,0xb4,0xac,0x23,0x01,0x00,0x00
+
+# ATT: sarxq %r19, %r23, %r27
+# INTEL: sarx r27, r23, r19
+0x62,0x6a,0xe6,0x00,0xf7,0xdf
+
+# ATT: sarxq %r19, 291(%r28,%r29,4), %r23
+# INTEL: sarx r23, qword ptr [r28 + 4*r29 + 291], r19
+0x62,0x8a,0xe2,0x00,0xf7,0xbc,0xac,0x23,0x01,0x00,0x00
+
+# ATT: shlxl %ecx, %edx, %r10d
+# INTEL: shlx r10d, edx, ecx
+0x62,0x72,0x75,0x08,0xf7,0xd2
+
+# ATT: shlxl %ecx, 123(%rax,%rbx,4), %edx
+# INTEL: shlx edx, dword ptr [rax + 4*rbx + 123], ecx
+0x62,0xf2,0x75,0x08,0xf7,0x94,0x98,0x7b,0x00,0x00,0x00
+
+# ATT: shlxq %r9, %r15, %r11
+# INTEL: shlx r11, r15, r9
+0x62,0x52,0xb5,0x08,0xf7,0xdf
+
+# ATT: shlxq %r9, 123(%rax,%rbx,4), %r15
+# INTEL: shlx r15, qword ptr [rax + 4*rbx + 123], r9
+0x62,0x72,0xb5,0x08,0xf7,0xbc,0x98,0x7b,0x00,0x00,0x00
+
+# ATT: shlxl %r18d, %r22d, %r26d
+# INTEL: shlx r26d, r22d, r18d
+0x62,0x6a,0x6d,0x00,0xf7,0xd6
+
+# ATT: shlxl %r18d, 291(%r28,%r29,4), %r22d
+# INTEL: shlx r22d, dword ptr [r28 + 4*r29 + 291], r18d
+0x62,0x8a,0x69,0x00,0xf7,0xb4,0xac,0x23,0x01,0x00,0x00
+
+# ATT: shlxq %r19, %r23, %r27
+# INTEL: shlx r27, r23, r19
+0x62,0x6a,0xe5,0x00,0xf7,0xdf
+
+# ATT: shlxq %r19, 291(%r28,%r29,4), %r23
+# INTEL: shlx r23, qword ptr [r28 + 4*r29 + 291], r19
+0x62,0x8a,0xe1,0x00,0xf7,0xbc,0xac,0x23,0x01,0x00,0x00
+
+# ATT: shrxl %ecx, %edx, %r10d
+# INTEL: shrx r10d, edx, ecx
+0x62,0x72,0x77,0x08,0xf7,0xd2
+
+# ATT: shrxl %ecx, 123(%rax,%rbx,4), %edx
+# INTEL: shrx edx, dword ptr [rax + 4*rbx + 123], ecx
+0x62,0xf2,0x77,0x08,0xf7,0x94,0x98,0x7b,0x00,0x00,0x00
+
+# ATT: shrxq %r9, %r15, %r11
+# INTEL: shrx r11, r15, r9
+0x62,0x52,0xb7,0x08,0xf7,0xdf
+
+# ATT: shrxq %r9, 123(%rax,%rbx,4), %r15
+# INTEL: shrx r15, qword ptr [rax + 4*rbx + 123], r9
+0x62,0x72,0xb7,0x08,0xf7,0xbc,0x98,0x7b,0x00,0x00,0x00
+
+# ATT: shrxl %r18d, %r22d, %r26d
+# INTEL: shrx r26d, r22d, r18d
+0x62,0x6a,0x6f,0x00,0xf7,0xd6
+
+# ATT: shrxl %r18d, 291(%r28,%r29,4), %r22d
+# INTEL: shrx r22d, dword ptr [r28 + 4*r29 + 291], r18d
+0x62,0x8a,0x6b,0x00,0xf7,0xb4,0xac,0x23,0x01,0x00,0x00
+
+# ATT: shrxq %r19, %r23, %r27
+# INTEL: shrx r27, r23, r19
+0x62,0x6a,0xe7,0x00,0xf7,0xdf
+
+# ATT: shrxq %r19, 291(%r28,%r29,4), %r23
+# INTEL: shrx r23, qword ptr [r28 + 4*r29 + 291], r19
+0x62,0x8a,0xe3,0x00,0xf7,0xbc,0xac,0x23,0x01,0x00,0x00
diff --git a/llvm/test/MC/Disassembler/X86/apx/cet.txt b/llvm/test/MC/Disassembler/X86/apx/cet.txt
new file mode 100644
index 00000000000000..1c9db6fea80874
--- /dev/null
+++ b/llvm/test/MC/Disassembler/X86/apx/cet.txt
@@ -0,0 +1,34 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT: wrssd %ecx, 123(%rax,%rbx,4)
+# INTEL: wrssd dword ptr [rax + 4*rbx + 123], ecx
+0x62,0xf4,0x7c,0x08,0x66,0x4c,0x98,0x7b
+
+# ATT: wrssd %r18d, 291(%r28,%r29,4)
+# INTEL: wrssd dword ptr [r28 + 4*r29 + 291], r18d
+0x62,0x8c,0x78,0x08,0x66,0x94,0xac,0x23,0x01,0x00,0x00
+
+# ATT: wrssq %r9, 123(%rax,%rbx,4)
+# INTEL: wrssq qword ptr [rax + 4*rbx + 123], r9
+0x62,0x74,0xfc,0x08,0x66,0x4c,0x98,0x7b
+
+# ATT: wrssq %r19, 291(%r28,%r29,4)
+# INTEL: wrssq qword ptr [r28 + 4*r29 + 291], r19
+0x62,0x8c,0xf8,0x08,0x66,0x9c,0xac,0x23,0x01,0x00,0x00
+
+# ATT: wrussd %ecx, 123(%rax,%rbx,4)
+# INTEL: wrussd dword ptr [rax + 4*rbx + 123], ecx
+0x62,0xf4,0x7d,0x08,0x65,0x4c,0x98,0x7b
+
+# ATT: wrussd %r18d, 291(%r28,%r29,4)
+# INTEL: wrussd dword ptr [r28 + 4*r29 + 291], r18d
+0x62,0x8c,0x79,0x08,0x65,0x94,0xac,0x23,0x01,0x00,0x00
+
+# ATT: wrussq %r9, 123(%rax,%rbx,4)
+# INTEL: wrussq qword ptr [rax + 4*rbx + 123], r9
+0x62,0x74,0xfd,0x08,0x65,0x4c,0x98,0x7b
+
+# ATT: wrussq %r19, 291(%r28,%r29,4)
+# INTEL: wrussq qword ptr [r28 + 4*r29 + 291], r19
+0x62,0x8c,0xf9,0x08,0x65,0x9c,0xac,0x23,0x01,0x00,0x00
diff --git a/llvm/test/MC/Disassembler/X86/apx/invept.txt b/llvm/test/MC/Disassembler/X86/apx/invept.txt
deleted file mode 100644
index dc6bcbbb05cca7..00000000000000
--- a/llvm/test/MC/Disassembler/X86/apx/invept.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
-# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
-
-# ATT: invept 123(%r28,%r29,4), %r19
-# INTEL: invept r19, xmmword ptr [r28 + 4*r29 + 123]
-0x62,0x8c,0x7a,0x08,0xf0,0x5c,0xac,0x7b
diff --git a/llvm/test/MC/Disassembler/X86/apx/invvpid.txt b/llvm/test/MC/Disassembler/X86/apx/invvpid.txt
deleted file mode 100644
index 05abc29b9b4679..00000000000000
--- a/llvm/test/MC/Disassembler/X86/apx/invvpid.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
-# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
-
-# ATT: invvpid 291(%r28,%r29,4), %r19
-# INTEL: invvpid r19, xmmword ptr [r28 + 4*r29 + 291]
-0x62,0x8c,0x7a,0x08,0xf1,0x9c,0xac,0x23,0x01,0x00,0x00
diff --git a/llvm/test/MC/Disassembler/X86/apx/movdir64b.txt b/llvm/test/MC/Disassembler/X86/apx/movdir64b.txt
index 81d8f49dbf69de..efb2f41056e321 100644
--- a/llvm/test/MC/Disassembler/X86/apx/movdir64b.txt
+++ b/llvm/test/MC/Disassembler/X86/apx/movdir64b.txt
@@ -1,6 +1,14 @@
# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+# ATT: movdir64b 123(%eax,%ebx,4), %ecx
+# INTEL: movdir64b ecx, zmmword ptr [eax + 4*ebx + 123]
+0x67,0x62,0xf4,0x7d,0x08,0xf8,0x4c,0x98,0x7b
+
+# ATT: movdir64b 123(%rax,%rbx,4), %r9
+# INTEL: movdir64b r9, zmmword ptr [rax + 4*rbx + 123]
+0x62,0x74,0x7d,0x08,0xf8,0x4c,0x98,0x7b
+
# ATT: movdir64b 291(%r28d,%r29d,4), %r18d
# INTEL: movdir64b r18d, zmmword ptr [r28d + 4*r29d + 291]
0x67,0x62,0x8c,0x79,0x08,0xf8,0x94,0xac,0x23,0x01,0x00,0x00
diff --git a/llvm/test/MC/Disassembler/X86/apx/movdiri.txt b/llvm/test/MC/Disassembler/X86/apx/movdiri.txt
index 997d016f0d2228..280d01e1cd0bbf 100644
--- a/llvm/test/MC/Disassembler/X86/apx/movdiri.txt
+++ b/llvm/test/MC/Disassembler/X86/apx/movdiri.txt
@@ -1,6 +1,14 @@
# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+# ATT: movdiri %ecx, 123(%eax,%ebx,4)
+# INTEL: movdiri dword ptr [eax + 4*ebx + 123], ecx
+0x67,0x62,0xf4,0x7c,0x08,0xf9,0x4c,0x98,0x7b
+
+# ATT: movdiri %r9, 123(%rax,%rbx,4)
+# INTEL: movdiri qword ptr [rax + 4*rbx + 123], r9
+0x62,0x74,0xfc,0x08,0xf9,0x4c,0x98,0x7b
+
# ATT: movdiri %r18d, 291(%r28,%r29,4)
# INTEL: movdiri dword ptr [r28 + 4*r29 + 291], r18d
0x62,0x8c,0x78,0x08,0xf9,0x94,0xac,0x23,0x01,0x00,0x00
diff --git a/llvm/test/MC/Disassembler/X86/apx/sha.txt b/llvm/test/MC/Disassembler/X86/apx/sha.txt
new file mode 100644
index 00000000000000..1697bdbbfdf61f
--- /dev/null
+++ b/llvm/test/MC/Disassembler/X86/apx/sha.txt
@@ -0,0 +1,110 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT: sha1msg1 %xmm13, %xmm12
+# INTEL: sha1msg1 xmm12, xmm13
+0x62,0x54,0x7c,0x08,0xd9,0xe5
+
+# ATT: sha1msg1 123(%rax,%rbx,4), %xmm12
+# INTEL: sha1msg1 xmm12, xmmword ptr [rax + 4*rbx + 123]
+0x62,0x74,0x7c,0x08,0xd9,0x64,0x98,0x7b
+
+# ATT: sha1msg1 %xmm13, %xmm12
+# INTEL: sha1msg1 xmm12, xmm13
+0x45,0x0f,0x38,0xc9,0xe5
+
+# ATT: sha1msg1 291(%r28,%r29,4), %xmm12
+# INTEL: sha1msg1 xmm12, xmmword ptr [r28 + 4*r29 + 291]
+0x62,0x1c,0x78,0x08,0xd9,0xa4,0xac,0x23,0x01,0x00,0x00
+
+# ATT: sha1msg2 %xmm13, %xmm12
+# INTEL: sha1msg2 xmm12, xmm13
+0x62,0x54,0x7c,0x08,0xda,0xe5
+
+# ATT: sha1msg2 123(%rax,%rbx,4), %xmm12
+# INTEL: sha1msg2 xmm12, xmmword ptr [rax + 4*rbx + 123]
+0x62,0x74,0x7c,0x08,0xda,0x64,0x98,0x7b
+
+# ATT: sha1msg2 %xmm13, %xmm12
+# INTEL: sha1msg2 xmm12, xmm13
+0x45,0x0f,0x38,0xca,0xe5
+
+# ATT: sha1msg2 291(%r28,%r29,4), %xmm12
+# INTEL: sha1msg2 xmm12, xmmword ptr [r28 + 4*r29 + 291]
+0x62,0x1c,0x78,0x08,0xda,0xa4,0xac,0x23,0x01,0x00,0x00
+
+# ATT: sha1nexte %xmm13, %xmm12
+# INTEL: sha1nexte xmm12, xmm13
+0x62,0x54,0x7c,0x08,0xd8,0xe5
+
+# ATT: sha1nexte 123(%rax,%rbx,4), %xmm12
+# INTEL: sha1nexte xmm12, xmmword ptr [rax + 4*rbx + 123]
+0x62,0x74,0x7c,0x08,0xd8,0x64,0x98,0x7b
+
+# ATT: sha1nexte %xmm13, %xmm12
+# INTEL: sha1nexte xmm12, xmm13
+0x45,0x0f,0x38,0xc8,0xe5
+
+# ATT: sha1nexte 291(%r28,%r29,4), %xmm12
+# INTEL: sha1nexte xmm12, xmmword ptr [r28 + 4*r29 + 291]
+0x62,0x1c,0x78,0x08,0xd8,0xa4,0xac,0x23,0x01,0x00,0x00
+
+# ATT: sha1rnds4 $123, %xmm13, %xmm12
+# INTEL: sha1rnds4 xmm12, xmm13, 123
+0x62,0x54,0x7c,0x08,0xd4,0xe5,0x7b
+
+# ATT: sha1rnds4 $123, 123(%rax,%rbx,4), %xmm12
+# INTEL: sha1rnds4 xmm12, xmmword ptr [rax + 4*rbx + 123], 123
+0x62,0x74,0x7c,0x08,0xd4,0x64,0x98,0x7b,0x7b
+
+# ATT: sha1rnds4 $123, %xmm13, %xmm12
+# INTEL: sha1rnds4 xmm12, xmm13, 123
+0x45,0x0f,0x3a,0xcc,0xe5,0x7b
+
+# ATT: sha1rnds4 $123, 291(%r28,%r29,4), %xmm12
+# INTEL: sha1rnds4 xmm12, xmmword ptr [r28 + 4*r29 + 291], 123
+0x62,0x1c,0x78,0x08,0xd4,0xa4,0xac,0x23,0x01,0x00,0x00,0x7b
+
+# ATT: sha256msg1 %xmm13, %xmm12
+# INTEL: sha256msg1 xmm12, xmm13
+0x62,0x54,0x7c,0x08,0xdc,0xe5
+
+# ATT: sha256msg1 123(%rax,%rbx,4), %xmm12
+# INTEL: sha256msg1 xmm12, xmmword ptr [rax + 4*rbx + 123]
+0x62,0x74,0x7c,0x08,0xdc,0x64,0x98,0x7b
+
+# ATT: sha256msg1 %xmm13, %xmm12
+# INTEL: sha256msg1 xmm12, xmm13
+0x45,0x0f,0x38,0xcc,0xe5
+
+# ATT: sha256msg1 291(%r28,%r29,4), %xmm12
+# INTEL: sha256msg1 xmm12, xmmword ptr [r28 + 4*r29 + 291]
+0x62,0x1c,0x78,0x08,0xdc,0xa4,0xac,0x23,0x01,0x00,0x00
+
+# ATT: sha256msg2 %xmm13, %xmm12
+# INTEL: sha256msg2 xmm12, xmm13
+0x62,0x54,0x7c,0x08,0xdd,0xe5
+
+# ATT: sha256msg2 123(%rax,%rbx,4), %xmm12
+# INTEL: sha256msg2 xmm12, xmmword ptr [rax + 4*rbx + 123]
+0x62,0x74,0x7c,0x08,0xdd,0x64,0x98,0x7b
+
+# ATT: sha256msg2 %xmm13, %xmm12
+# INTEL: sha256msg2 xmm12, xmm13
+0x45,0x0f,0x38,0xcd,0xe5
+
+# ATT: sha256msg2 291(%r28,%r29,4), %xmm12
+# INTEL: sha256msg2 xmm12, xmmword ptr [r28 + 4*r29 + 291]
+0x62,0x1c,0x78,0x08,0xdd,0xa4,0xac,0x23,0x01,0x00,0x00
+
+# ATT: sha256rnds2 %xmm0, 123(%rax,%rbx,4), %xmm12
+# INTEL: sha256rnds2 xmm12, xmmword ptr [rax + 4*rbx + 123], xmm0
+0x62,0x74,0x7c,0x08,0xdb,0x64,0x98,0x7b
+
+# ATT: sha256rnds2 %xmm0, %xmm13, %xmm12
+# INTEL: sha256rnds2 xmm12, xmm13, xmm0
+0x45,0x0f,0x38,0xcb,0xe5
+
+# ATT: sha256rnds2 %xmm0, 291(%r28,%r29,4), %xmm12
+# INTEL: sha256rnds2 xmm12, xmmword ptr [r28 + 4*r29 + 291], xmm0
+0x62,0x1c,0x78,0x08,0xdb,0xa4,0xac,0x23,0x01,0x00,0x00
diff --git a/llvm/test/MC/Disassembler/X86/apx/sha1msg1.txt b/llvm/test/MC/Disassembler/X86/apx/sha1msg1.txt
deleted file mode 100644
index 1c94fa88a3d3cf..00000000000000
--- a/llvm/test/MC/Disassembler/X86/apx/sha1msg1.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
-# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
-
-# ATT: sha1msg1 %xmm13, %xmm12
-# INTEL: sha1msg1 xmm12, xmm13
-0x45,0x0f,0x38,0xc9,0xe5
-
-# ATT: sha1msg1 291(%r28,%r29,4), %xmm12
-# INTEL: sha1msg1 xmm12, xmmword ptr [r28 + 4*r29 + 291]
-0x62,0x1c,0x78,0x08,0xd9,0xa4,0xac,0x23,0x01,0x00,0x00
diff --git a/llvm/test/MC/Disassembler/X86/apx/sha1msg2.txt b/llvm/test/MC/Disassembler/X86/apx/sha1msg2.txt
deleted file mode 100644
index 5fd17d9f326006..00000000000000
--- a/llvm/test/MC/Disassembler/X86/apx/sha1msg2.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
-# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
-
-# ATT: sha1msg2 %xmm13, %xmm12
-# INTEL: sha1msg2 xmm12, xmm13
-0x45,0x0f,0x38,0xca,0xe5
-
-# ATT: sha1msg2 291(%r28,%r29,4), %xmm12
-# INTEL: sha1msg2 xmm12, xmmword ptr [r28 + 4*r29 + 291]
-0x62,0x1c,0x78,0x08,0xda,0xa4,0xac,0x23,0x01,0x00,0x00
diff --git a/llvm/test/MC/Disassembler/X86/apx/sha1nexte.txt b/llvm/test/MC/Disassembler/X86/apx/sha1nexte.txt
deleted file mode 100644
index 3c5eae3d7177fc..00000000000000
--- a/llvm/test/MC/Disassembler/X86/apx/sha1nexte.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
-# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
-
-# ATT: sha1nexte %xmm13, %xmm12
-# INTEL: sha1nexte xmm12, xmm13
-0x45,0x0f,0x38,0xc8,0xe5
-
-# ATT: sha1nexte 291(%r28,%r29,4), %xmm12
-# INTEL: sha1nexte xmm12, xmmword ptr [r28 + 4*r29 + 291]
-0x62,0x1c,0x78,0x08,0xd8,0xa4,0xac,0x23,0x01,0x00,0x00
diff --git a/llvm/test/MC/Disassembler/X86/apx/sha1rnds4.txt b/llvm/test/MC/Disassembler/X86/apx/sha1rnds4.txt
deleted file mode 100644
index a05f17739606ac..00000000000000
--- a/llvm/test/MC/Disassembler/X86/apx/sha1rnds4.txt
+++ /dev/null
@@ -1,10...
[truncated]
|
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Opcode values changed, trivial fix.
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As suggested in #76210, this patch re-organize the mc tests for apx promoted instrs, instr tests within same cpuid would be listed in one test.
Also add explicit prefix {evex} tests and 8 displacement memory test, promoted instrs need set No_CD8 to avoid AVX512 compress encoding.