RegisterPressure: Uncomment out assert #87405
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This appears to have been accidentally commented out in 91b5cf8
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This fails in quite a few AMDGPU tests |
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@llvm/pr-subscribers-llvm-regalloc Author: Matt Arsenault (arsenm) ChangesThis appears to have been accidentally commented out in 91b5cf8 Full diff: https://github.com/llvm/llvm-project/pull/87405.diff 1 Files Affected:
diff --git a/llvm/lib/CodeGen/RegisterPressure.cpp b/llvm/lib/CodeGen/RegisterPressure.cpp
index f86aa3a167202f..9320abd8963b12 100644
--- a/llvm/lib/CodeGen/RegisterPressure.cpp
+++ b/llvm/lib/CodeGen/RegisterPressure.cpp
@@ -64,7 +64,7 @@ static void increaseSetPressure(std::vector<unsigned> &CurrSetPressure,
static void decreaseSetPressure(std::vector<unsigned> &CurrSetPressure,
const MachineRegisterInfo &MRI, Register Reg,
LaneBitmask PrevMask, LaneBitmask NewMask) {
- //assert((NewMask & !PrevMask) == 0 && "Must not add bits");
+ assert((NewMask & ~PrevMask).none() && "Must not add bits");
if (NewMask.any() || PrevMask.none())
return;
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kparzysz
reviewed
Apr 10, 2024
| @@ -64,7 +64,7 @@ static void increaseSetPressure(std::vector<unsigned> &CurrSetPressure, | |||
| static void decreaseSetPressure(std::vector<unsigned> &CurrSetPressure, | |||
| const MachineRegisterInfo &MRI, Register Reg, | |||
| LaneBitmask PrevMask, LaneBitmask NewMask) { | |||
| //assert((NewMask & !PrevMask) == 0 && "Must not add bits"); | |||
| assert((NewMask & ~PrevMask).none() && "Must not add bits"); | |||
There was a problem hiding this comment.
Line 783 should most likely be PreviousMask |= LiveOut. When I do that, the following tests fail in "check-llvm-codegen":
Failed Tests (21):
LLVM :: CodeGen/AMDGPU/amdgpu.private-memory.ll
LLVM :: CodeGen/AMDGPU/coalesce-vgpr-alignment.ll
LLVM :: CodeGen/AMDGPU/dag-divergence-atomic.ll
LLVM :: CodeGen/AMDGPU/global_atomics.ll
LLVM :: CodeGen/AMDGPU/global_atomics_i64.ll
LLVM :: CodeGen/AMDGPU/insert_vector_dynelt.ll
LLVM :: CodeGen/AMDGPU/itofp.i128.ll
LLVM :: CodeGen/AMDGPU/lds-misaligned-bug.ll
LLVM :: CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.atomic.ll
LLVM :: CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.ll
LLVM :: CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.atomic.ll
LLVM :: CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.ll
LLVM :: CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.ll
LLVM :: CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.ll
LLVM :: CodeGen/AMDGPU/load-global-i32.ll
LLVM :: CodeGen/AMDGPU/load-local-i32.ll
LLVM :: CodeGen/AMDGPU/merge-stores.ll
LLVM :: CodeGen/AMDGPU/promote-alloca-globals.ll
LLVM :: CodeGen/AMDGPU/sgpr-copy.ll
LLVM :: CodeGen/AMDGPU/spill-agpr.ll
LLVM :: CodeGen/AMDGPU/v_mac.ll
At least one test fails because UseMask has more bits set in it than LiveLanes in RegPressureTracker::bumpUpwardPressure. I think there is some issue with how the lane masks are calculated/adjusted.
The tests I used is
llc -mtriple=amdgcn -mcpu=tonga -amdgpu-atomic-optimizer-strategy=None -mattr=-flat-for-global -verify-machineinstrs llvm/test/CodeGen/AMDGPU/global_atomics.ll -o -
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It wasn't accidental, tests were failing with that assertion, even back then. |
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I think there is some issue in the register operand collection/liveness adjustment in cases where the same virtual register is used and defined in an instruction. Still investigating. |
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Replaced by #88892 |
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This appears to have been accidentally commented out in 91b5cf8