[GlobalIsel] Import vscale #88240
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[GlobalIsel] Import vscale #88240
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@llvm/pr-subscribers-llvm-globalisel Author: Thorsten Schütt (tschuett) ChangesFull diff: https://github.com/llvm/llvm-project/pull/88240.diff 2 Files Affected:
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index 312e564f5d8022..56ee197dd05be4 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -2550,6 +2550,11 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
MIRBuilder.buildInstr(TargetOpcode::G_RESET_FPMODE, {}, {});
return true;
}
+ case Intrinsic::vscale: {
+ MIRBuilder.buildInstr(TargetOpcode::G_VSCALE, {getOrCreateVReg(CI)}, {})
+ .addImm(1);
+ return true;
+ }
case Intrinsic::prefetch: {
Value *Addr = CI.getOperand(0);
unsigned RW = cast<ConstantInt>(CI.getOperand(1))->getZExtValue();
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-vscale.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-vscale.ll
new file mode 100644
index 00000000000000..cdc98d15e0726a
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-vscale.ll
@@ -0,0 +1,52 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+; RUN: llc -O0 -mtriple=aarch64-linux-gnu -global-isel -stop-after=irtranslator %s -o - | FileCheck %s
+
+define i64 @call_vscale_i64() {
+ ; CHECK-LABEL: name: call_vscale_i64
+ ; CHECK: bb.1.entry:
+ ; CHECK-NEXT: [[VSCALE:%[0-9]+]]:_(s64) = G_VSCALE 1
+ ; CHECK-NEXT: $x0 = COPY [[VSCALE]](s64)
+ ; CHECK-NEXT: RET_ReallyLR implicit $x0
+entry:
+ %vscale = call i64 @llvm.vscale.64()
+ ret i64 %vscale
+}
+
+define i64 @call_vscale_i32() {
+ ; CHECK-LABEL: name: call_vscale_i32
+ ; CHECK: bb.1.entry:
+ ; CHECK-NEXT: [[VSCALE:%[0-9]+]]:_(s32) = G_VSCALE 1
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[VSCALE]](s32)
+ ; CHECK-NEXT: $x0 = COPY [[ZEXT]](s64)
+ ; CHECK-NEXT: RET_ReallyLR implicit $x0
+entry:
+ %vscale = call i32 @llvm.vscale.32()
+ %zext = zext i32 %vscale to i64
+ ret i64 %zext
+}
+
+define i64 @call_vscale_i16() {
+ ; CHECK-LABEL: name: call_vscale_i16
+ ; CHECK: bb.1.entry:
+ ; CHECK-NEXT: [[VSCALE:%[0-9]+]]:_(s16) = G_VSCALE 1
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[VSCALE]](s16)
+ ; CHECK-NEXT: $x0 = COPY [[ZEXT]](s64)
+ ; CHECK-NEXT: RET_ReallyLR implicit $x0
+entry:
+ %vscale = call i16 @llvm.vscale.16()
+ %zext = zext i16 %vscale to i64
+ ret i64 %zext
+}
+
+define i64 @call_vscale_i8() {
+ ; CHECK-LABEL: name: call_vscale_i8
+ ; CHECK: bb.1.entry:
+ ; CHECK-NEXT: [[VSCALE:%[0-9]+]]:_(s8) = G_VSCALE 1
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[VSCALE]](s8)
+ ; CHECK-NEXT: $x0 = COPY [[ZEXT]](s64)
+ ; CHECK-NEXT: RET_ReallyLR implicit $x0
+entry:
+ %vscale = call i8 @llvm.vscale.8()
+ %zext = zext i8 %vscale to i64
+ ret i64 %zext
+}
|
|
@llvm/pr-subscribers-backend-aarch64 Author: Thorsten Schütt (tschuett) ChangesFull diff: https://github.com/llvm/llvm-project/pull/88240.diff 2 Files Affected:
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index 312e564f5d8022..56ee197dd05be4 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -2550,6 +2550,11 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
MIRBuilder.buildInstr(TargetOpcode::G_RESET_FPMODE, {}, {});
return true;
}
+ case Intrinsic::vscale: {
+ MIRBuilder.buildInstr(TargetOpcode::G_VSCALE, {getOrCreateVReg(CI)}, {})
+ .addImm(1);
+ return true;
+ }
case Intrinsic::prefetch: {
Value *Addr = CI.getOperand(0);
unsigned RW = cast<ConstantInt>(CI.getOperand(1))->getZExtValue();
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-vscale.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-vscale.ll
new file mode 100644
index 00000000000000..cdc98d15e0726a
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-vscale.ll
@@ -0,0 +1,52 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+; RUN: llc -O0 -mtriple=aarch64-linux-gnu -global-isel -stop-after=irtranslator %s -o - | FileCheck %s
+
+define i64 @call_vscale_i64() {
+ ; CHECK-LABEL: name: call_vscale_i64
+ ; CHECK: bb.1.entry:
+ ; CHECK-NEXT: [[VSCALE:%[0-9]+]]:_(s64) = G_VSCALE 1
+ ; CHECK-NEXT: $x0 = COPY [[VSCALE]](s64)
+ ; CHECK-NEXT: RET_ReallyLR implicit $x0
+entry:
+ %vscale = call i64 @llvm.vscale.64()
+ ret i64 %vscale
+}
+
+define i64 @call_vscale_i32() {
+ ; CHECK-LABEL: name: call_vscale_i32
+ ; CHECK: bb.1.entry:
+ ; CHECK-NEXT: [[VSCALE:%[0-9]+]]:_(s32) = G_VSCALE 1
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[VSCALE]](s32)
+ ; CHECK-NEXT: $x0 = COPY [[ZEXT]](s64)
+ ; CHECK-NEXT: RET_ReallyLR implicit $x0
+entry:
+ %vscale = call i32 @llvm.vscale.32()
+ %zext = zext i32 %vscale to i64
+ ret i64 %zext
+}
+
+define i64 @call_vscale_i16() {
+ ; CHECK-LABEL: name: call_vscale_i16
+ ; CHECK: bb.1.entry:
+ ; CHECK-NEXT: [[VSCALE:%[0-9]+]]:_(s16) = G_VSCALE 1
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[VSCALE]](s16)
+ ; CHECK-NEXT: $x0 = COPY [[ZEXT]](s64)
+ ; CHECK-NEXT: RET_ReallyLR implicit $x0
+entry:
+ %vscale = call i16 @llvm.vscale.16()
+ %zext = zext i16 %vscale to i64
+ ret i64 %zext
+}
+
+define i64 @call_vscale_i8() {
+ ; CHECK-LABEL: name: call_vscale_i8
+ ; CHECK: bb.1.entry:
+ ; CHECK-NEXT: [[VSCALE:%[0-9]+]]:_(s8) = G_VSCALE 1
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[VSCALE]](s8)
+ ; CHECK-NEXT: $x0 = COPY [[ZEXT]](s64)
+ ; CHECK-NEXT: RET_ReallyLR implicit $x0
+entry:
+ %vscale = call i8 @llvm.vscale.8()
+ %zext = zext i8 %vscale to i64
+ ret i64 %zext
+}
|
arsenm
reviewed
Apr 12, 2024
Comment on lines
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to
2559
| MIRBuilder.buildInstr(TargetOpcode::G_VSCALE, {getOrCreateVReg(CI)}, {}) | ||
| .addCImm(CInt); |
There was a problem hiding this comment.
Move this into a buildVScale in the MIRBuilder?
arsenm
approved these changes
Apr 12, 2024
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#84542