[clang] Introduce target-specific Sema components
#93179
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Endilll
added
backend:ARM
backend:AMDGPU
backend:BPF
backend:Hexagon
backend:MIPS
backend:PowerPC
backend:SystemZ
backend:WebAssembly
clang:frontend
Endilll
requested review from
cor3ntin,
RKSimon,
AaronBallman,
miyuki,
jdoerfert,
erichkeane and
maryammo
llvmbot
added
clang
|
@llvm/pr-subscribers-backend-powerpc @llvm/pr-subscribers-backend-amdgpu Author: Vlad Serebrennikov (Endilll) ChangesThis patch introduces I decided to bundle target-specific components together because of their low impact on Somewhat accidentally, I also moved Wasm- and AMDGPU-specific function from Patch is 349.72 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/93179.diff 30 Files Affected:
diff --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h
index 057ff61ccc644..e19509c811805 100644
--- a/clang/include/clang/Sema/Sema.h
+++ b/clang/include/clang/Sema/Sema.h
@@ -67,6 +67,7 @@
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/SmallVector.h"
+#include "llvm/ADT/StringExtras.h"
#include "llvm/ADT/TinyPtrVector.h"
#include <deque>
#include <memory>
@@ -168,15 +169,25 @@ class Preprocessor;
class PseudoDestructorTypeStorage;
class PseudoObjectExpr;
class QualType;
+class SemaAMDGPU;
+class SemaARM;
+class SemaBPF;
class SemaCodeCompletion;
class SemaCUDA;
class SemaHLSL;
+class SemaHexagon;
+class SemaLoongArch;
+class SemaMIPS;
+class SemaNVPTX;
class SemaObjC;
class SemaOpenACC;
class SemaOpenMP;
+class SemaPPC;
class SemaPseudoObject;
class SemaRISCV;
class SemaSYCL;
+class SemaSystemZ;
+class SemaWasm;
class SemaX86;
class StandardConversionSequence;
class Stmt;
@@ -993,6 +1004,21 @@ class Sema final : public SemaBase {
/// CurContext - This is the current declaration context of parsing.
DeclContext *CurContext;
+ SemaAMDGPU &AMDGPU() {
+ assert(AMDGPUPtr);
+ return *AMDGPUPtr;
+ }
+
+ SemaARM &ARM() {
+ assert(ARMPtr);
+ return *ARMPtr;
+ }
+
+ SemaBPF &BPF() {
+ assert(BPFPtr);
+ return *BPFPtr;
+ }
+
SemaCodeCompletion &CodeCompletion() {
assert(CodeCompletionPtr);
return *CodeCompletionPtr;
@@ -1008,6 +1034,26 @@ class Sema final : public SemaBase {
return *HLSLPtr;
}
+ SemaHexagon &Hexagon() {
+ assert(HexagonPtr);
+ return *HexagonPtr;
+ }
+
+ SemaLoongArch &LoongArch() {
+ assert(LoongArchPtr);
+ return *LoongArchPtr;
+ }
+
+ SemaMIPS &MIPS() {
+ assert(MIPSPtr);
+ return *MIPSPtr;
+ }
+
+ SemaNVPTX &NVPTX() {
+ assert(NVPTXPtr);
+ return *NVPTXPtr;
+ }
+
SemaObjC &ObjC() {
assert(ObjCPtr);
return *ObjCPtr;
@@ -1023,6 +1069,11 @@ class Sema final : public SemaBase {
return *OpenMPPtr;
}
+ SemaPPC &PPC() {
+ assert(PPCPtr);
+ return *PPCPtr;
+ }
+
SemaPseudoObject &PseudoObject() {
assert(PseudoObjectPtr);
return *PseudoObjectPtr;
@@ -1038,6 +1089,16 @@ class Sema final : public SemaBase {
return *SYCLPtr;
}
+ SemaSystemZ &SystemZ() {
+ assert(SystemZPtr);
+ return *SystemZPtr;
+ }
+
+ SemaWasm &Wasm() {
+ assert(WasmPtr);
+ return *WasmPtr;
+ }
+
SemaX86 &X86() {
assert(X86Ptr);
return *X86Ptr;
@@ -1073,15 +1134,25 @@ class Sema final : public SemaBase {
mutable IdentifierInfo *Ident_super;
+ std::unique_ptr<SemaAMDGPU> AMDGPUPtr;
+ std::unique_ptr<SemaARM> ARMPtr;
+ std::unique_ptr<SemaBPF> BPFPtr;
std::unique_ptr<SemaCodeCompletion> CodeCompletionPtr;
std::unique_ptr<SemaCUDA> CUDAPtr;
std::unique_ptr<SemaHLSL> HLSLPtr;
+ std::unique_ptr<SemaHexagon> HexagonPtr;
+ std::unique_ptr<SemaLoongArch> LoongArchPtr;
+ std::unique_ptr<SemaMIPS> MIPSPtr;
+ std::unique_ptr<SemaNVPTX> NVPTXPtr;
std::unique_ptr<SemaObjC> ObjCPtr;
std::unique_ptr<SemaOpenACC> OpenACCPtr;
std::unique_ptr<SemaOpenMP> OpenMPPtr;
+ std::unique_ptr<SemaPPC> PPCPtr;
std::unique_ptr<SemaPseudoObject> PseudoObjectPtr;
std::unique_ptr<SemaRISCV> RISCVPtr;
std::unique_ptr<SemaSYCL> SYCLPtr;
+ std::unique_ptr<SemaSystemZ> SystemZPtr;
+ std::unique_ptr<SemaWasm> WasmPtr;
std::unique_ptr<SemaX86> X86Ptr;
///@}
@@ -2074,6 +2145,8 @@ class Sema final : public SemaBase {
unsigned MaxArgCount);
bool checkArgCount(CallExpr *Call, unsigned DesiredArgCount);
+ bool ValueIsRunOfOnes(CallExpr *TheCall, unsigned ArgNum);
+
private:
void CheckArrayAccess(const Expr *BaseExpr, const Expr *IndexExpr,
const ArraySubscriptExpr *ASE = nullptr,
@@ -2087,8 +2160,6 @@ class Sema final : public SemaBase {
ArrayRef<const Expr *> Args,
const FunctionProtoType *Proto, SourceLocation Loc);
- void checkAIXMemberAlignment(SourceLocation Loc, const Expr *Arg);
-
void CheckArgAlignment(SourceLocation Loc, NamedDecl *FDecl,
StringRef ParamName, QualType ArgTy, QualType ParamTy);
@@ -2102,54 +2173,13 @@ class Sema final : public SemaBase {
void checkFortifiedBuiltinMemoryFunction(FunctionDecl *FD, CallExpr *TheCall);
- bool CheckARMBuiltinExclusiveCall(unsigned BuiltinID, CallExpr *TheCall,
- unsigned MaxWidth);
- bool CheckNeonBuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID,
- CallExpr *TheCall);
- bool CheckMVEBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall);
- bool CheckSVEBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall);
- bool ParseSVEImmChecks(CallExpr *TheCall,
- SmallVector<std::tuple<int, int, int>, 3> &ImmChecks);
- bool CheckSMEBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall);
- bool CheckCDEBuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID,
- CallExpr *TheCall);
- bool CheckARMCoprocessorImmediate(const TargetInfo &TI, const Expr *CoprocArg,
- bool WantCDE);
- bool CheckARMBuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID,
- CallExpr *TheCall);
-
- bool CheckAArch64BuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID,
- CallExpr *TheCall);
- bool CheckBPFBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall);
- bool CheckHexagonBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall);
- bool CheckHexagonBuiltinArgument(unsigned BuiltinID, CallExpr *TheCall);
- bool CheckMipsBuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID,
- CallExpr *TheCall);
- bool CheckMipsBuiltinCpu(const TargetInfo &TI, unsigned BuiltinID,
- CallExpr *TheCall);
- bool CheckMipsBuiltinArgument(unsigned BuiltinID, CallExpr *TheCall);
- bool CheckSystemZBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall);
- bool CheckPPCBuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID,
- CallExpr *TheCall);
- bool CheckAMDGCNBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall);
-
- bool CheckLoongArchBuiltinFunctionCall(const TargetInfo &TI,
- unsigned BuiltinID, CallExpr *TheCall);
- bool CheckWebAssemblyBuiltinFunctionCall(const TargetInfo &TI,
- unsigned BuiltinID,
- CallExpr *TheCall);
- bool CheckNVPTXBuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID,
- CallExpr *TheCall);
-
bool BuiltinVAStart(unsigned BuiltinID, CallExpr *TheCall);
bool BuiltinVAStartARMMicrosoft(CallExpr *Call);
bool BuiltinUnorderedCompare(CallExpr *TheCall, unsigned BuiltinID);
bool BuiltinFPClassification(CallExpr *TheCall, unsigned NumArgs,
unsigned BuiltinID);
bool BuiltinComplex(CallExpr *TheCall);
- bool BuiltinVSX(CallExpr *TheCall);
bool BuiltinOSLogFormat(CallExpr *TheCall);
- bool ValueIsRunOfOnes(CallExpr *TheCall, unsigned ArgNum);
bool BuiltinPrefetch(CallExpr *TheCall);
bool BuiltinAllocaWithAlign(CallExpr *TheCall);
@@ -2162,13 +2192,6 @@ class Sema final : public SemaBase {
ExprResult BuiltinNontemporalOverloaded(ExprResult TheCallResult);
ExprResult AtomicOpsOverloaded(ExprResult TheCallResult,
AtomicExpr::AtomicOp Op);
- bool BuiltinARMSpecialReg(unsigned BuiltinID, CallExpr *TheCall, int ArgNum,
- unsigned ExpectedFieldNum, bool AllowName);
- bool BuiltinARMMemoryTaggingCall(unsigned BuiltinID, CallExpr *TheCall);
- bool BuiltinPPCMMACall(CallExpr *TheCall, unsigned BuiltinID,
- const char *TypeDesc);
-
- bool CheckPPCMMAType(QualType Type, SourceLocation TypeLoc);
bool BuiltinElementwiseMath(CallExpr *TheCall);
bool BuiltinElementwiseTernaryMath(CallExpr *TheCall,
@@ -2185,16 +2208,6 @@ class Sema final : public SemaBase {
ExprResult BuiltinMatrixColumnMajorStore(CallExpr *TheCall,
ExprResult CallResult);
- // WebAssembly builtin handling.
- bool BuiltinWasmRefNullExtern(CallExpr *TheCall);
- bool BuiltinWasmRefNullFunc(CallExpr *TheCall);
- bool BuiltinWasmTableGet(CallExpr *TheCall);
- bool BuiltinWasmTableSet(CallExpr *TheCall);
- bool BuiltinWasmTableSize(CallExpr *TheCall);
- bool BuiltinWasmTableGrow(CallExpr *TheCall);
- bool BuiltinWasmTableFill(CallExpr *TheCall);
- bool BuiltinWasmTableCopy(CallExpr *TheCall);
-
bool CheckFormatArguments(const FormatAttr *Format,
ArrayRef<const Expr *> Args, bool IsCXXMember,
VariadicCallType CallType, SourceLocation Loc,
@@ -3548,6 +3561,56 @@ class Sema final : public SemaBase {
BuiltinFunction
};
+ /// A helper function to provide Attribute Location for the Attr types
+ /// AND the ParsedAttr.
+ template <typename AttrInfo>
+ static std::enable_if_t<std::is_base_of_v<Attr, AttrInfo>, SourceLocation>
+ getAttrLoc(const AttrInfo &AL) {
+ return AL.getLocation();
+ }
+ SourceLocation getAttrLoc(const ParsedAttr &AL);
+
+ /// If Expr is a valid integer constant, get the value of the integer
+ /// expression and return success or failure. May output an error.
+ ///
+ /// Negative argument is implicitly converted to unsigned, unless
+ /// \p StrictlyUnsigned is true.
+ template <typename AttrInfo>
+ bool checkUInt32Argument(const AttrInfo &AI, const Expr *Expr, uint32_t &Val,
+ unsigned Idx = UINT_MAX,
+ bool StrictlyUnsigned = false) {
+ std::optional<llvm::APSInt> I = llvm::APSInt(32);
+ if (Expr->isTypeDependent() ||
+ !(I = Expr->getIntegerConstantExpr(Context))) {
+ if (Idx != UINT_MAX)
+ Diag(getAttrLoc(AI), diag::err_attribute_argument_n_type)
+ << &AI << Idx << AANT_ArgumentIntegerConstant
+ << Expr->getSourceRange();
+ else
+ Diag(getAttrLoc(AI), diag::err_attribute_argument_type)
+ << &AI << AANT_ArgumentIntegerConstant << Expr->getSourceRange();
+ return false;
+ }
+
+ if (!I->isIntN(32)) {
+ Diag(Expr->getExprLoc(), diag::err_ice_too_large)
+ << toString(*I, 10, false) << 32 << /* Unsigned */ 1;
+ return false;
+ }
+
+ if (StrictlyUnsigned && I->isSigned() && I->isNegative()) {
+ Diag(getAttrLoc(AI), diag::err_attribute_requires_positive_integer)
+ << &AI << /*non-negative*/ 1;
+ return false;
+ }
+
+ Val = (uint32_t)I->getZExtValue();
+ return true;
+ }
+
+ bool isFunctionOrMethod(const Decl *D);
+ bool isFunctionOrMethodOrBlock(const Decl *D);
+
/// WeakTopLevelDecl - Translation-unit scoped declarations generated by
/// \#pragma weak during processing of other Decls.
/// I couldn't figure out a clean way to generate these in-line, so
@@ -3705,41 +3768,6 @@ class Sema final : public SemaBase {
BTFDeclTagAttr *mergeBTFDeclTagAttr(Decl *D, const BTFDeclTagAttr &AL);
- WebAssemblyImportNameAttr *
- mergeImportNameAttr(Decl *D, const WebAssemblyImportNameAttr &AL);
- WebAssemblyImportModuleAttr *
- mergeImportModuleAttr(Decl *D, const WebAssemblyImportModuleAttr &AL);
-
- /// Create an AMDGPUWavesPerEUAttr attribute.
- AMDGPUFlatWorkGroupSizeAttr *
- CreateAMDGPUFlatWorkGroupSizeAttr(const AttributeCommonInfo &CI, Expr *Min,
- Expr *Max);
-
- /// addAMDGPUFlatWorkGroupSizeAttr - Adds an amdgpu_flat_work_group_size
- /// attribute to a particular declaration.
- void addAMDGPUFlatWorkGroupSizeAttr(Decl *D, const AttributeCommonInfo &CI,
- Expr *Min, Expr *Max);
-
- /// Create an AMDGPUWavesPerEUAttr attribute.
- AMDGPUWavesPerEUAttr *
- CreateAMDGPUWavesPerEUAttr(const AttributeCommonInfo &CI, Expr *Min,
- Expr *Max);
-
- /// addAMDGPUWavePersEUAttr - Adds an amdgpu_waves_per_eu attribute to a
- /// particular declaration.
- void addAMDGPUWavesPerEUAttr(Decl *D, const AttributeCommonInfo &CI,
- Expr *Min, Expr *Max);
-
- /// Create an AMDGPUMaxNumWorkGroupsAttr attribute.
- AMDGPUMaxNumWorkGroupsAttr *
- CreateAMDGPUMaxNumWorkGroupsAttr(const AttributeCommonInfo &CI, Expr *XExpr,
- Expr *YExpr, Expr *ZExpr);
-
- /// addAMDGPUMaxNumWorkGroupsAttr - Adds an amdgpu_max_num_work_groups
- /// attribute to a particular declaration.
- void addAMDGPUMaxNumWorkGroupsAttr(Decl *D, const AttributeCommonInfo &CI,
- Expr *XExpr, Expr *YExpr, Expr *ZExpr);
-
DLLImportAttr *mergeDLLImportAttr(Decl *D, const AttributeCommonInfo &CI);
DLLExportAttr *mergeDLLExportAttr(Decl *D, const AttributeCommonInfo &CI);
MSInheritanceAttr *mergeMSInheritanceAttr(Decl *D,
diff --git a/clang/include/clang/Sema/SemaAMDGPU.h b/clang/include/clang/Sema/SemaAMDGPU.h
new file mode 100644
index 0000000000000..969078f552c6a
--- /dev/null
+++ b/clang/include/clang/Sema/SemaAMDGPU.h
@@ -0,0 +1,68 @@
+//===----- SemaAMDGPU.h --- AMDGPU target-specific routines ---*- C++ -*---===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+/// \file
+/// This file declares semantic analysis functions specific to AMDGPU.
+///
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_CLANG_SEMA_SEMAAMDGPU_H
+#define LLVM_CLANG_SEMA_SEMAAMDGPU_H
+
+#include "clang/AST/Attr.h"
+#include "clang/AST/DeclBase.h"
+#include "clang/AST/Expr.h"
+#include "clang/Basic/AttributeCommonInfo.h"
+#include "clang/Sema/ParsedAttr.h"
+#include "clang/Sema/SemaBase.h"
+
+namespace clang {
+class SemaAMDGPU : public SemaBase {
+public:
+ SemaAMDGPU(Sema &S);
+
+ bool CheckAMDGCNBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall);
+
+ /// Create an AMDGPUWavesPerEUAttr attribute.
+ AMDGPUFlatWorkGroupSizeAttr *
+ CreateAMDGPUFlatWorkGroupSizeAttr(const AttributeCommonInfo &CI, Expr *Min,
+ Expr *Max);
+
+ /// addAMDGPUFlatWorkGroupSizeAttr - Adds an amdgpu_flat_work_group_size
+ /// attribute to a particular declaration.
+ void addAMDGPUFlatWorkGroupSizeAttr(Decl *D, const AttributeCommonInfo &CI,
+ Expr *Min, Expr *Max);
+
+ /// Create an AMDGPUWavesPerEUAttr attribute.
+ AMDGPUWavesPerEUAttr *
+ CreateAMDGPUWavesPerEUAttr(const AttributeCommonInfo &CI, Expr *Min,
+ Expr *Max);
+
+ /// addAMDGPUWavePersEUAttr - Adds an amdgpu_waves_per_eu attribute to a
+ /// particular declaration.
+ void addAMDGPUWavesPerEUAttr(Decl *D, const AttributeCommonInfo &CI,
+ Expr *Min, Expr *Max);
+
+ /// Create an AMDGPUMaxNumWorkGroupsAttr attribute.
+ AMDGPUMaxNumWorkGroupsAttr *
+ CreateAMDGPUMaxNumWorkGroupsAttr(const AttributeCommonInfo &CI, Expr *XExpr,
+ Expr *YExpr, Expr *ZExpr);
+
+ /// addAMDGPUMaxNumWorkGroupsAttr - Adds an amdgpu_max_num_work_groups
+ /// attribute to a particular declaration.
+ void addAMDGPUMaxNumWorkGroupsAttr(Decl *D, const AttributeCommonInfo &CI,
+ Expr *XExpr, Expr *YExpr, Expr *ZExpr);
+
+ void handleAMDGPUWavesPerEUAttr(Decl *D, const ParsedAttr &AL);
+ void handleAMDGPUNumSGPRAttr(Decl *D, const ParsedAttr &AL);
+ void handleAMDGPUNumVGPRAttr(Decl *D, const ParsedAttr &AL);
+ void handleAMDGPUMaxNumWorkGroupsAttr(Decl *D, const ParsedAttr &AL);
+ void handleAMDGPUFlatWorkGroupSizeAttr(Decl *D, const ParsedAttr &AL);
+};
+} // namespace clang
+
+#endif // LLVM_CLANG_SEMA_SEMAAMDGPU_H
diff --git a/clang/include/clang/Sema/SemaARM.h b/clang/include/clang/Sema/SemaARM.h
new file mode 100644
index 0000000000000..02698a33abd55
--- /dev/null
+++ b/clang/include/clang/Sema/SemaARM.h
@@ -0,0 +1,63 @@
+//===----- SemaARM.h ------- ARM target-specific routines -----*- C++ -*---===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+/// \file
+/// This file declares semantic analysis functions specific to ARM.
+///
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_CLANG_SEMA_SEMAARM_H
+#define LLVM_CLANG_SEMA_SEMAARM_H
+
+#include "clang/AST/Expr.h"
+#include "clang/Basic/TargetInfo.h"
+#include "clang/Sema/SemaBase.h"
+#include "llvm/ADT/SmallVector.h"
+#include <tuple>
+
+namespace clang {
+
+class SemaARM : public SemaBase {
+public:
+ SemaARM(Sema &S);
+
+ enum ArmStreamingType {
+ ArmNonStreaming,
+ ArmStreaming,
+ ArmStreamingCompatible,
+ ArmStreamingOrSVE2p1
+ };
+
+ bool CheckARMBuiltinExclusiveCall(unsigned BuiltinID, CallExpr *TheCall,
+ unsigned MaxWidth);
+ bool CheckNeonBuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID,
+ CallExpr *TheCall);
+ bool CheckMVEBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall);
+ bool CheckSVEBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall);
+ bool
+ ParseSVEImmChecks(CallExpr *TheCall,
+ llvm::SmallVector<std::tuple<int, int, int>, 3> &ImmChecks);
+ bool CheckSMEBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall);
+ bool CheckCDEBuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID,
+ CallExpr *TheCall);
+ bool CheckARMCoprocessorImmediate(const TargetInfo &TI, const Expr *CoprocArg,
+ bool WantCDE);
+ bool CheckARMBuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID,
+ CallExpr *TheCall);
+
+ bool CheckAArch64BuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID,
+ CallExpr *TheCall);
+ bool BuiltinARMSpecialReg(unsigned BuiltinID, CallExpr *TheCall, int ArgNum,
+ unsigned ExpectedFieldNum, bool AllowName);
+ bool BuiltinARMMemoryTaggingCall(unsigned BuiltinID, CallExpr *TheCall);
+};
+
+SemaARM::ArmStreamingType getArmStreamingFnType(const FunctionDecl *FD);
+
+} // namespace clang
+
+#endif // LLVM_CLANG_SEMA_SEMAARM_H
diff --git a/clang/include/clang/Sema/SemaBPF.h b/clang/include/clang/Sema/SemaBPF.h
new file mode 100644
index 0000000000000..a3bf59128d254
--- /dev/null
+++ b/clang/include/clang/Sema/SemaBPF.h
@@ -0,0 +1,28 @@
+//===----- SemaBPF.h ------- BPF target-specific routines -----*- C++ -*---===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+/// \file
+/// This file declares semantic analysis functions specific to BPF.
+///
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_CLANG_SEMA_SEMABPF_H
+#define LLVM_CLANG_SEMA_SEMABPF_H
+
+#include "clang/AST/Expr.h"
+#include "clang/Sema/SemaBase.h"
+
+namespace clang {
+class SemaBPF : public SemaBase {
+public:
+ SemaBPF(Sema &S);
+
+ bool CheckBPFBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall);
+};
+} // namespace clang
+
+#endif // LLVM_CLANG_SEMA_SEMABPF_H
diff --git a/clang/include/clang/Sema/SemaHexagon.h b/clang/include/clang/Sema/SemaHexagon.h
new file mode 100644
index 0000000000000..2d4a04f824bc2
--- /dev/null
+++ b/clang/include/clang/Sema/SemaHexagon.h
@@ -0,0 +1,29 @@
+//===----- SemaHexagon.h -- Hexagon target-specific routines --...
[truncated]
|
|
@llvm/pr-subscribers-backend-systemz Author: Vlad Serebrennikov (Endilll) ChangesThis patch introduces I decided to bundle target-specific components together because of their low impact on Somewhat accidentally, I also moved Wasm- and AMDGPU-specific function from Patch is 349.72 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/93179.diff 30 Files Affected:
diff --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h
index 057ff61ccc644..e19509c811805 100644
--- a/clang/include/clang/Sema/Sema.h
+++ b/clang/include/clang/Sema/Sema.h
@@ -67,6 +67,7 @@
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/SmallVector.h"
+#include "llvm/ADT/StringExtras.h"
#include "llvm/ADT/TinyPtrVector.h"
#include <deque>
#include <memory>
@@ -168,15 +169,25 @@ class Preprocessor;
class PseudoDestructorTypeStorage;
class PseudoObjectExpr;
class QualType;
+class SemaAMDGPU;
+class SemaARM;
+class SemaBPF;
class SemaCodeCompletion;
class SemaCUDA;
class SemaHLSL;
+class SemaHexagon;
+class SemaLoongArch;
+class SemaMIPS;
+class SemaNVPTX;
class SemaObjC;
class SemaOpenACC;
class SemaOpenMP;
+class SemaPPC;
class SemaPseudoObject;
class SemaRISCV;
class SemaSYCL;
+class SemaSystemZ;
+class SemaWasm;
class SemaX86;
class StandardConversionSequence;
class Stmt;
@@ -993,6 +1004,21 @@ class Sema final : public SemaBase {
/// CurContext - This is the current declaration context of parsing.
DeclContext *CurContext;
+ SemaAMDGPU &AMDGPU() {
+ assert(AMDGPUPtr);
+ return *AMDGPUPtr;
+ }
+
+ SemaARM &ARM() {
+ assert(ARMPtr);
+ return *ARMPtr;
+ }
+
+ SemaBPF &BPF() {
+ assert(BPFPtr);
+ return *BPFPtr;
+ }
+
SemaCodeCompletion &CodeCompletion() {
assert(CodeCompletionPtr);
return *CodeCompletionPtr;
@@ -1008,6 +1034,26 @@ class Sema final : public SemaBase {
return *HLSLPtr;
}
+ SemaHexagon &Hexagon() {
+ assert(HexagonPtr);
+ return *HexagonPtr;
+ }
+
+ SemaLoongArch &LoongArch() {
+ assert(LoongArchPtr);
+ return *LoongArchPtr;
+ }
+
+ SemaMIPS &MIPS() {
+ assert(MIPSPtr);
+ return *MIPSPtr;
+ }
+
+ SemaNVPTX &NVPTX() {
+ assert(NVPTXPtr);
+ return *NVPTXPtr;
+ }
+
SemaObjC &ObjC() {
assert(ObjCPtr);
return *ObjCPtr;
@@ -1023,6 +1069,11 @@ class Sema final : public SemaBase {
return *OpenMPPtr;
}
+ SemaPPC &PPC() {
+ assert(PPCPtr);
+ return *PPCPtr;
+ }
+
SemaPseudoObject &PseudoObject() {
assert(PseudoObjectPtr);
return *PseudoObjectPtr;
@@ -1038,6 +1089,16 @@ class Sema final : public SemaBase {
return *SYCLPtr;
}
+ SemaSystemZ &SystemZ() {
+ assert(SystemZPtr);
+ return *SystemZPtr;
+ }
+
+ SemaWasm &Wasm() {
+ assert(WasmPtr);
+ return *WasmPtr;
+ }
+
SemaX86 &X86() {
assert(X86Ptr);
return *X86Ptr;
@@ -1073,15 +1134,25 @@ class Sema final : public SemaBase {
mutable IdentifierInfo *Ident_super;
+ std::unique_ptr<SemaAMDGPU> AMDGPUPtr;
+ std::unique_ptr<SemaARM> ARMPtr;
+ std::unique_ptr<SemaBPF> BPFPtr;
std::unique_ptr<SemaCodeCompletion> CodeCompletionPtr;
std::unique_ptr<SemaCUDA> CUDAPtr;
std::unique_ptr<SemaHLSL> HLSLPtr;
+ std::unique_ptr<SemaHexagon> HexagonPtr;
+ std::unique_ptr<SemaLoongArch> LoongArchPtr;
+ std::unique_ptr<SemaMIPS> MIPSPtr;
+ std::unique_ptr<SemaNVPTX> NVPTXPtr;
std::unique_ptr<SemaObjC> ObjCPtr;
std::unique_ptr<SemaOpenACC> OpenACCPtr;
std::unique_ptr<SemaOpenMP> OpenMPPtr;
+ std::unique_ptr<SemaPPC> PPCPtr;
std::unique_ptr<SemaPseudoObject> PseudoObjectPtr;
std::unique_ptr<SemaRISCV> RISCVPtr;
std::unique_ptr<SemaSYCL> SYCLPtr;
+ std::unique_ptr<SemaSystemZ> SystemZPtr;
+ std::unique_ptr<SemaWasm> WasmPtr;
std::unique_ptr<SemaX86> X86Ptr;
///@}
@@ -2074,6 +2145,8 @@ class Sema final : public SemaBase {
unsigned MaxArgCount);
bool checkArgCount(CallExpr *Call, unsigned DesiredArgCount);
+ bool ValueIsRunOfOnes(CallExpr *TheCall, unsigned ArgNum);
+
private:
void CheckArrayAccess(const Expr *BaseExpr, const Expr *IndexExpr,
const ArraySubscriptExpr *ASE = nullptr,
@@ -2087,8 +2160,6 @@ class Sema final : public SemaBase {
ArrayRef<const Expr *> Args,
const FunctionProtoType *Proto, SourceLocation Loc);
- void checkAIXMemberAlignment(SourceLocation Loc, const Expr *Arg);
-
void CheckArgAlignment(SourceLocation Loc, NamedDecl *FDecl,
StringRef ParamName, QualType ArgTy, QualType ParamTy);
@@ -2102,54 +2173,13 @@ class Sema final : public SemaBase {
void checkFortifiedBuiltinMemoryFunction(FunctionDecl *FD, CallExpr *TheCall);
- bool CheckARMBuiltinExclusiveCall(unsigned BuiltinID, CallExpr *TheCall,
- unsigned MaxWidth);
- bool CheckNeonBuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID,
- CallExpr *TheCall);
- bool CheckMVEBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall);
- bool CheckSVEBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall);
- bool ParseSVEImmChecks(CallExpr *TheCall,
- SmallVector<std::tuple<int, int, int>, 3> &ImmChecks);
- bool CheckSMEBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall);
- bool CheckCDEBuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID,
- CallExpr *TheCall);
- bool CheckARMCoprocessorImmediate(const TargetInfo &TI, const Expr *CoprocArg,
- bool WantCDE);
- bool CheckARMBuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID,
- CallExpr *TheCall);
-
- bool CheckAArch64BuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID,
- CallExpr *TheCall);
- bool CheckBPFBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall);
- bool CheckHexagonBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall);
- bool CheckHexagonBuiltinArgument(unsigned BuiltinID, CallExpr *TheCall);
- bool CheckMipsBuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID,
- CallExpr *TheCall);
- bool CheckMipsBuiltinCpu(const TargetInfo &TI, unsigned BuiltinID,
- CallExpr *TheCall);
- bool CheckMipsBuiltinArgument(unsigned BuiltinID, CallExpr *TheCall);
- bool CheckSystemZBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall);
- bool CheckPPCBuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID,
- CallExpr *TheCall);
- bool CheckAMDGCNBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall);
-
- bool CheckLoongArchBuiltinFunctionCall(const TargetInfo &TI,
- unsigned BuiltinID, CallExpr *TheCall);
- bool CheckWebAssemblyBuiltinFunctionCall(const TargetInfo &TI,
- unsigned BuiltinID,
- CallExpr *TheCall);
- bool CheckNVPTXBuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID,
- CallExpr *TheCall);
-
bool BuiltinVAStart(unsigned BuiltinID, CallExpr *TheCall);
bool BuiltinVAStartARMMicrosoft(CallExpr *Call);
bool BuiltinUnorderedCompare(CallExpr *TheCall, unsigned BuiltinID);
bool BuiltinFPClassification(CallExpr *TheCall, unsigned NumArgs,
unsigned BuiltinID);
bool BuiltinComplex(CallExpr *TheCall);
- bool BuiltinVSX(CallExpr *TheCall);
bool BuiltinOSLogFormat(CallExpr *TheCall);
- bool ValueIsRunOfOnes(CallExpr *TheCall, unsigned ArgNum);
bool BuiltinPrefetch(CallExpr *TheCall);
bool BuiltinAllocaWithAlign(CallExpr *TheCall);
@@ -2162,13 +2192,6 @@ class Sema final : public SemaBase {
ExprResult BuiltinNontemporalOverloaded(ExprResult TheCallResult);
ExprResult AtomicOpsOverloaded(ExprResult TheCallResult,
AtomicExpr::AtomicOp Op);
- bool BuiltinARMSpecialReg(unsigned BuiltinID, CallExpr *TheCall, int ArgNum,
- unsigned ExpectedFieldNum, bool AllowName);
- bool BuiltinARMMemoryTaggingCall(unsigned BuiltinID, CallExpr *TheCall);
- bool BuiltinPPCMMACall(CallExpr *TheCall, unsigned BuiltinID,
- const char *TypeDesc);
-
- bool CheckPPCMMAType(QualType Type, SourceLocation TypeLoc);
bool BuiltinElementwiseMath(CallExpr *TheCall);
bool BuiltinElementwiseTernaryMath(CallExpr *TheCall,
@@ -2185,16 +2208,6 @@ class Sema final : public SemaBase {
ExprResult BuiltinMatrixColumnMajorStore(CallExpr *TheCall,
ExprResult CallResult);
- // WebAssembly builtin handling.
- bool BuiltinWasmRefNullExtern(CallExpr *TheCall);
- bool BuiltinWasmRefNullFunc(CallExpr *TheCall);
- bool BuiltinWasmTableGet(CallExpr *TheCall);
- bool BuiltinWasmTableSet(CallExpr *TheCall);
- bool BuiltinWasmTableSize(CallExpr *TheCall);
- bool BuiltinWasmTableGrow(CallExpr *TheCall);
- bool BuiltinWasmTableFill(CallExpr *TheCall);
- bool BuiltinWasmTableCopy(CallExpr *TheCall);
-
bool CheckFormatArguments(const FormatAttr *Format,
ArrayRef<const Expr *> Args, bool IsCXXMember,
VariadicCallType CallType, SourceLocation Loc,
@@ -3548,6 +3561,56 @@ class Sema final : public SemaBase {
BuiltinFunction
};
+ /// A helper function to provide Attribute Location for the Attr types
+ /// AND the ParsedAttr.
+ template <typename AttrInfo>
+ static std::enable_if_t<std::is_base_of_v<Attr, AttrInfo>, SourceLocation>
+ getAttrLoc(const AttrInfo &AL) {
+ return AL.getLocation();
+ }
+ SourceLocation getAttrLoc(const ParsedAttr &AL);
+
+ /// If Expr is a valid integer constant, get the value of the integer
+ /// expression and return success or failure. May output an error.
+ ///
+ /// Negative argument is implicitly converted to unsigned, unless
+ /// \p StrictlyUnsigned is true.
+ template <typename AttrInfo>
+ bool checkUInt32Argument(const AttrInfo &AI, const Expr *Expr, uint32_t &Val,
+ unsigned Idx = UINT_MAX,
+ bool StrictlyUnsigned = false) {
+ std::optional<llvm::APSInt> I = llvm::APSInt(32);
+ if (Expr->isTypeDependent() ||
+ !(I = Expr->getIntegerConstantExpr(Context))) {
+ if (Idx != UINT_MAX)
+ Diag(getAttrLoc(AI), diag::err_attribute_argument_n_type)
+ << &AI << Idx << AANT_ArgumentIntegerConstant
+ << Expr->getSourceRange();
+ else
+ Diag(getAttrLoc(AI), diag::err_attribute_argument_type)
+ << &AI << AANT_ArgumentIntegerConstant << Expr->getSourceRange();
+ return false;
+ }
+
+ if (!I->isIntN(32)) {
+ Diag(Expr->getExprLoc(), diag::err_ice_too_large)
+ << toString(*I, 10, false) << 32 << /* Unsigned */ 1;
+ return false;
+ }
+
+ if (StrictlyUnsigned && I->isSigned() && I->isNegative()) {
+ Diag(getAttrLoc(AI), diag::err_attribute_requires_positive_integer)
+ << &AI << /*non-negative*/ 1;
+ return false;
+ }
+
+ Val = (uint32_t)I->getZExtValue();
+ return true;
+ }
+
+ bool isFunctionOrMethod(const Decl *D);
+ bool isFunctionOrMethodOrBlock(const Decl *D);
+
/// WeakTopLevelDecl - Translation-unit scoped declarations generated by
/// \#pragma weak during processing of other Decls.
/// I couldn't figure out a clean way to generate these in-line, so
@@ -3705,41 +3768,6 @@ class Sema final : public SemaBase {
BTFDeclTagAttr *mergeBTFDeclTagAttr(Decl *D, const BTFDeclTagAttr &AL);
- WebAssemblyImportNameAttr *
- mergeImportNameAttr(Decl *D, const WebAssemblyImportNameAttr &AL);
- WebAssemblyImportModuleAttr *
- mergeImportModuleAttr(Decl *D, const WebAssemblyImportModuleAttr &AL);
-
- /// Create an AMDGPUWavesPerEUAttr attribute.
- AMDGPUFlatWorkGroupSizeAttr *
- CreateAMDGPUFlatWorkGroupSizeAttr(const AttributeCommonInfo &CI, Expr *Min,
- Expr *Max);
-
- /// addAMDGPUFlatWorkGroupSizeAttr - Adds an amdgpu_flat_work_group_size
- /// attribute to a particular declaration.
- void addAMDGPUFlatWorkGroupSizeAttr(Decl *D, const AttributeCommonInfo &CI,
- Expr *Min, Expr *Max);
-
- /// Create an AMDGPUWavesPerEUAttr attribute.
- AMDGPUWavesPerEUAttr *
- CreateAMDGPUWavesPerEUAttr(const AttributeCommonInfo &CI, Expr *Min,
- Expr *Max);
-
- /// addAMDGPUWavePersEUAttr - Adds an amdgpu_waves_per_eu attribute to a
- /// particular declaration.
- void addAMDGPUWavesPerEUAttr(Decl *D, const AttributeCommonInfo &CI,
- Expr *Min, Expr *Max);
-
- /// Create an AMDGPUMaxNumWorkGroupsAttr attribute.
- AMDGPUMaxNumWorkGroupsAttr *
- CreateAMDGPUMaxNumWorkGroupsAttr(const AttributeCommonInfo &CI, Expr *XExpr,
- Expr *YExpr, Expr *ZExpr);
-
- /// addAMDGPUMaxNumWorkGroupsAttr - Adds an amdgpu_max_num_work_groups
- /// attribute to a particular declaration.
- void addAMDGPUMaxNumWorkGroupsAttr(Decl *D, const AttributeCommonInfo &CI,
- Expr *XExpr, Expr *YExpr, Expr *ZExpr);
-
DLLImportAttr *mergeDLLImportAttr(Decl *D, const AttributeCommonInfo &CI);
DLLExportAttr *mergeDLLExportAttr(Decl *D, const AttributeCommonInfo &CI);
MSInheritanceAttr *mergeMSInheritanceAttr(Decl *D,
diff --git a/clang/include/clang/Sema/SemaAMDGPU.h b/clang/include/clang/Sema/SemaAMDGPU.h
new file mode 100644
index 0000000000000..969078f552c6a
--- /dev/null
+++ b/clang/include/clang/Sema/SemaAMDGPU.h
@@ -0,0 +1,68 @@
+//===----- SemaAMDGPU.h --- AMDGPU target-specific routines ---*- C++ -*---===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+/// \file
+/// This file declares semantic analysis functions specific to AMDGPU.
+///
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_CLANG_SEMA_SEMAAMDGPU_H
+#define LLVM_CLANG_SEMA_SEMAAMDGPU_H
+
+#include "clang/AST/Attr.h"
+#include "clang/AST/DeclBase.h"
+#include "clang/AST/Expr.h"
+#include "clang/Basic/AttributeCommonInfo.h"
+#include "clang/Sema/ParsedAttr.h"
+#include "clang/Sema/SemaBase.h"
+
+namespace clang {
+class SemaAMDGPU : public SemaBase {
+public:
+ SemaAMDGPU(Sema &S);
+
+ bool CheckAMDGCNBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall);
+
+ /// Create an AMDGPUWavesPerEUAttr attribute.
+ AMDGPUFlatWorkGroupSizeAttr *
+ CreateAMDGPUFlatWorkGroupSizeAttr(const AttributeCommonInfo &CI, Expr *Min,
+ Expr *Max);
+
+ /// addAMDGPUFlatWorkGroupSizeAttr - Adds an amdgpu_flat_work_group_size
+ /// attribute to a particular declaration.
+ void addAMDGPUFlatWorkGroupSizeAttr(Decl *D, const AttributeCommonInfo &CI,
+ Expr *Min, Expr *Max);
+
+ /// Create an AMDGPUWavesPerEUAttr attribute.
+ AMDGPUWavesPerEUAttr *
+ CreateAMDGPUWavesPerEUAttr(const AttributeCommonInfo &CI, Expr *Min,
+ Expr *Max);
+
+ /// addAMDGPUWavePersEUAttr - Adds an amdgpu_waves_per_eu attribute to a
+ /// particular declaration.
+ void addAMDGPUWavesPerEUAttr(Decl *D, const AttributeCommonInfo &CI,
+ Expr *Min, Expr *Max);
+
+ /// Create an AMDGPUMaxNumWorkGroupsAttr attribute.
+ AMDGPUMaxNumWorkGroupsAttr *
+ CreateAMDGPUMaxNumWorkGroupsAttr(const AttributeCommonInfo &CI, Expr *XExpr,
+ Expr *YExpr, Expr *ZExpr);
+
+ /// addAMDGPUMaxNumWorkGroupsAttr - Adds an amdgpu_max_num_work_groups
+ /// attribute to a particular declaration.
+ void addAMDGPUMaxNumWorkGroupsAttr(Decl *D, const AttributeCommonInfo &CI,
+ Expr *XExpr, Expr *YExpr, Expr *ZExpr);
+
+ void handleAMDGPUWavesPerEUAttr(Decl *D, const ParsedAttr &AL);
+ void handleAMDGPUNumSGPRAttr(Decl *D, const ParsedAttr &AL);
+ void handleAMDGPUNumVGPRAttr(Decl *D, const ParsedAttr &AL);
+ void handleAMDGPUMaxNumWorkGroupsAttr(Decl *D, const ParsedAttr &AL);
+ void handleAMDGPUFlatWorkGroupSizeAttr(Decl *D, const ParsedAttr &AL);
+};
+} // namespace clang
+
+#endif // LLVM_CLANG_SEMA_SEMAAMDGPU_H
diff --git a/clang/include/clang/Sema/SemaARM.h b/clang/include/clang/Sema/SemaARM.h
new file mode 100644
index 0000000000000..02698a33abd55
--- /dev/null
+++ b/clang/include/clang/Sema/SemaARM.h
@@ -0,0 +1,63 @@
+//===----- SemaARM.h ------- ARM target-specific routines -----*- C++ -*---===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+/// \file
+/// This file declares semantic analysis functions specific to ARM.
+///
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_CLANG_SEMA_SEMAARM_H
+#define LLVM_CLANG_SEMA_SEMAARM_H
+
+#include "clang/AST/Expr.h"
+#include "clang/Basic/TargetInfo.h"
+#include "clang/Sema/SemaBase.h"
+#include "llvm/ADT/SmallVector.h"
+#include <tuple>
+
+namespace clang {
+
+class SemaARM : public SemaBase {
+public:
+ SemaARM(Sema &S);
+
+ enum ArmStreamingType {
+ ArmNonStreaming,
+ ArmStreaming,
+ ArmStreamingCompatible,
+ ArmStreamingOrSVE2p1
+ };
+
+ bool CheckARMBuiltinExclusiveCall(unsigned BuiltinID, CallExpr *TheCall,
+ unsigned MaxWidth);
+ bool CheckNeonBuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID,
+ CallExpr *TheCall);
+ bool CheckMVEBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall);
+ bool CheckSVEBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall);
+ bool
+ ParseSVEImmChecks(CallExpr *TheCall,
+ llvm::SmallVector<std::tuple<int, int, int>, 3> &ImmChecks);
+ bool CheckSMEBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall);
+ bool CheckCDEBuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID,
+ CallExpr *TheCall);
+ bool CheckARMCoprocessorImmediate(const TargetInfo &TI, const Expr *CoprocArg,
+ bool WantCDE);
+ bool CheckARMBuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID,
+ CallExpr *TheCall);
+
+ bool CheckAArch64BuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID,
+ CallExpr *TheCall);
+ bool BuiltinARMSpecialReg(unsigned BuiltinID, CallExpr *TheCall, int ArgNum,
+ unsigned ExpectedFieldNum, bool AllowName);
+ bool BuiltinARMMemoryTaggingCall(unsigned BuiltinID, CallExpr *TheCall);
+};
+
+SemaARM::ArmStreamingType getArmStreamingFnType(const FunctionDecl *FD);
+
+} // namespace clang
+
+#endif // LLVM_CLANG_SEMA_SEMAARM_H
diff --git a/clang/include/clang/Sema/SemaBPF.h b/clang/include/clang/Sema/SemaBPF.h
new file mode 100644
index 0000000000000..a3bf59128d254
--- /dev/null
+++ b/clang/include/clang/Sema/SemaBPF.h
@@ -0,0 +1,28 @@
+//===----- SemaBPF.h ------- BPF target-specific routines -----*- C++ -*---===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+/// \file
+/// This file declares semantic analysis functions specific to BPF.
+///
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_CLANG_SEMA_SEMABPF_H
+#define LLVM_CLANG_SEMA_SEMABPF_H
+
+#include "clang/AST/Expr.h"
+#include "clang/Sema/SemaBase.h"
+
+namespace clang {
+class SemaBPF : public SemaBase {
+public:
+ SemaBPF(Sema &S);
+
+ bool CheckBPFBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall);
+};
+} // namespace clang
+
+#endif // LLVM_CLANG_SEMA_SEMABPF_H
diff --git a/clang/include/clang/Sema/SemaHexagon.h b/clang/include/clang/Sema/SemaHexagon.h
new file mode 100644
index 0000000000000..2d4a04f824bc2
--- /dev/null
+++ b/clang/include/clang/Sema/SemaHexagon.h
@@ -0,0 +1,29 @@
+//===----- SemaHexagon.h -- Hexagon target-specific routines --...
[truncated]
|
You can test this locally with the following command:git-clang-format --diff 1bf1f93d94cb395e04329b17a4fcff65b4ff8122 e2a279bfade14090e1b56e8254a48078d7abffa4 -- clang/include/clang/Sema/Attr.h clang/include/clang/Sema/SemaAMDGPU.h clang/include/clang/Sema/SemaARM.h clang/include/clang/Sema/SemaBPF.h clang/include/clang/Sema/SemaHexagon.h clang/include/clang/Sema/SemaLoongArch.h clang/include/clang/Sema/SemaMIPS.h clang/include/clang/Sema/SemaNVPTX.h clang/include/clang/Sema/SemaPPC.h clang/include/clang/Sema/SemaSystemZ.h clang/include/clang/Sema/SemaWasm.h clang/lib/Sema/SemaAMDGPU.cpp clang/lib/Sema/SemaARM.cpp clang/lib/Sema/SemaBPF.cpp clang/lib/Sema/SemaHexagon.cpp clang/lib/Sema/SemaLoongArch.cpp clang/lib/Sema/SemaMIPS.cpp clang/lib/Sema/SemaNVPTX.cpp clang/lib/Sema/SemaPPC.cpp clang/lib/Sema/SemaSystemZ.cpp clang/lib/Sema/SemaWasm.cpp clang/include/clang/Sema/Sema.h clang/lib/Parse/ParseOpenMP.cpp clang/lib/Sema/Sema.cpp clang/lib/Sema/SemaChecking.cpp clang/lib/Sema/SemaDecl.cpp clang/lib/Sema/SemaDeclAttr.cpp clang/lib/Sema/SemaExprCXX.cpp clang/lib/Sema/SemaTemplateInstantiateDecl.cpp clang/utils/TableGen/MveEmitter.cppView the diff from clang-format here.diff --git a/clang/lib/Sema/SemaARM.cpp b/clang/lib/Sema/SemaARM.cpp
index da37ccef05..b38d59df35 100644
--- a/clang/lib/Sema/SemaARM.cpp
+++ b/clang/lib/Sema/SemaARM.cpp
@@ -577,7 +577,8 @@ static void checkArmStreamingBuiltin(Sema &S, CallExpr *TheCall,
BuiltinType == SemaARM::ArmNonStreaming)
S.Diag(TheCall->getBeginLoc(), diag::warn_attribute_arm_sm_incompat_builtin)
<< TheCall->getSourceRange() << "streaming";
- else if (FnType == SemaARM::ArmNonStreaming && BuiltinType == SemaARM::ArmStreaming)
+ else if (FnType == SemaARM::ArmNonStreaming &&
+ BuiltinType == SemaARM::ArmStreaming)
S.Diag(TheCall->getBeginLoc(), diag::warn_attribute_arm_sm_incompat_builtin)
<< TheCall->getSourceRange() << "non-streaming";
else if (FnType == SemaARM::ArmStreamingCompatible &&
@@ -1075,11 +1076,18 @@ bool SemaARM::CheckAArch64BuiltinFunctionCall(const TargetInfo &TI,
// range check them here.
unsigned i = 0, l = 0, u = 0;
switch (BuiltinID) {
- default: return false;
+ default:
+ return false;
case AArch64::BI__builtin_arm_dmb:
case AArch64::BI__builtin_arm_dsb:
- case AArch64::BI__builtin_arm_isb: l = 0; u = 15; break;
- case AArch64::BI__builtin_arm_tcancel: l = 0; u = 65535; break;
+ case AArch64::BI__builtin_arm_isb:
+ l = 0;
+ u = 15;
+ break;
+ case AArch64::BI__builtin_arm_tcancel:
+ l = 0;
+ u = 65535;
+ break;
}
return SemaRef.BuiltinConstantArgRange(TheCall, i, l, u + l);
diff --git a/clang/lib/Sema/SemaHexagon.cpp b/clang/lib/Sema/SemaHexagon.cpp
index 5c921c0bc9..25331fc3b3 100644
--- a/clang/lib/Sema/SemaHexagon.cpp
+++ b/clang/lib/Sema/SemaHexagon.cpp
@@ -35,214 +35,200 @@ bool SemaHexagon::CheckHexagonBuiltinArgument(unsigned BuiltinID,
};
static BuiltinInfo Infos[] = {
- { Hexagon::BI__builtin_circ_ldd, {{ 3, true, 4, 3 }} },
- { Hexagon::BI__builtin_circ_ldw, {{ 3, true, 4, 2 }} },
- { Hexagon::BI__builtin_circ_ldh, {{ 3, true, 4, 1 }} },
- { Hexagon::BI__builtin_circ_lduh, {{ 3, true, 4, 1 }} },
- { Hexagon::BI__builtin_circ_ldb, {{ 3, true, 4, 0 }} },
- { Hexagon::BI__builtin_circ_ldub, {{ 3, true, 4, 0 }} },
- { Hexagon::BI__builtin_circ_std, {{ 3, true, 4, 3 }} },
- { Hexagon::BI__builtin_circ_stw, {{ 3, true, 4, 2 }} },
- { Hexagon::BI__builtin_circ_sth, {{ 3, true, 4, 1 }} },
- { Hexagon::BI__builtin_circ_sthhi, {{ 3, true, 4, 1 }} },
- { Hexagon::BI__builtin_circ_stb, {{ 3, true, 4, 0 }} },
+ {Hexagon::BI__builtin_circ_ldd, {{3, true, 4, 3}}},
+ {Hexagon::BI__builtin_circ_ldw, {{3, true, 4, 2}}},
+ {Hexagon::BI__builtin_circ_ldh, {{3, true, 4, 1}}},
+ {Hexagon::BI__builtin_circ_lduh, {{3, true, 4, 1}}},
+ {Hexagon::BI__builtin_circ_ldb, {{3, true, 4, 0}}},
+ {Hexagon::BI__builtin_circ_ldub, {{3, true, 4, 0}}},
+ {Hexagon::BI__builtin_circ_std, {{3, true, 4, 3}}},
+ {Hexagon::BI__builtin_circ_stw, {{3, true, 4, 2}}},
+ {Hexagon::BI__builtin_circ_sth, {{3, true, 4, 1}}},
+ {Hexagon::BI__builtin_circ_sthhi, {{3, true, 4, 1}}},
+ {Hexagon::BI__builtin_circ_stb, {{3, true, 4, 0}}},
- { Hexagon::BI__builtin_HEXAGON_L2_loadrub_pci, {{ 1, true, 4, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_L2_loadrb_pci, {{ 1, true, 4, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_L2_loadruh_pci, {{ 1, true, 4, 1 }} },
- { Hexagon::BI__builtin_HEXAGON_L2_loadrh_pci, {{ 1, true, 4, 1 }} },
- { Hexagon::BI__builtin_HEXAGON_L2_loadri_pci, {{ 1, true, 4, 2 }} },
- { Hexagon::BI__builtin_HEXAGON_L2_loadrd_pci, {{ 1, true, 4, 3 }} },
- { Hexagon::BI__builtin_HEXAGON_S2_storerb_pci, {{ 1, true, 4, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S2_storerh_pci, {{ 1, true, 4, 1 }} },
- { Hexagon::BI__builtin_HEXAGON_S2_storerf_pci, {{ 1, true, 4, 1 }} },
- { Hexagon::BI__builtin_HEXAGON_S2_storeri_pci, {{ 1, true, 4, 2 }} },
- { Hexagon::BI__builtin_HEXAGON_S2_storerd_pci, {{ 1, true, 4, 3 }} },
+ {Hexagon::BI__builtin_HEXAGON_L2_loadrub_pci, {{1, true, 4, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_L2_loadrb_pci, {{1, true, 4, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_L2_loadruh_pci, {{1, true, 4, 1}}},
+ {Hexagon::BI__builtin_HEXAGON_L2_loadrh_pci, {{1, true, 4, 1}}},
+ {Hexagon::BI__builtin_HEXAGON_L2_loadri_pci, {{1, true, 4, 2}}},
+ {Hexagon::BI__builtin_HEXAGON_L2_loadrd_pci, {{1, true, 4, 3}}},
+ {Hexagon::BI__builtin_HEXAGON_S2_storerb_pci, {{1, true, 4, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S2_storerh_pci, {{1, true, 4, 1}}},
+ {Hexagon::BI__builtin_HEXAGON_S2_storerf_pci, {{1, true, 4, 1}}},
+ {Hexagon::BI__builtin_HEXAGON_S2_storeri_pci, {{1, true, 4, 2}}},
+ {Hexagon::BI__builtin_HEXAGON_S2_storerd_pci, {{1, true, 4, 3}}},
- { Hexagon::BI__builtin_HEXAGON_A2_combineii, {{ 1, true, 8, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_A2_tfrih, {{ 1, false, 16, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_A2_tfril, {{ 1, false, 16, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_A2_tfrpi, {{ 0, true, 8, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_A4_bitspliti, {{ 1, false, 5, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_A4_cmpbeqi, {{ 1, false, 8, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_A4_cmpbgti, {{ 1, true, 8, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_A4_cround_ri, {{ 1, false, 5, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_A4_round_ri, {{ 1, false, 5, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_A4_round_ri_sat, {{ 1, false, 5, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_A4_vcmpbeqi, {{ 1, false, 8, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_A4_vcmpbgti, {{ 1, true, 8, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_A4_vcmpbgtui, {{ 1, false, 7, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_A4_vcmpheqi, {{ 1, true, 8, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_A4_vcmphgti, {{ 1, true, 8, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_A4_vcmphgtui, {{ 1, false, 7, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_A4_vcmpweqi, {{ 1, true, 8, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_A4_vcmpwgti, {{ 1, true, 8, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_A4_vcmpwgtui, {{ 1, false, 7, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_C2_bitsclri, {{ 1, false, 6, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_C2_muxii, {{ 2, true, 8, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_C4_nbitsclri, {{ 1, false, 6, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_F2_dfclass, {{ 1, false, 5, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_F2_dfimm_n, {{ 0, false, 10, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_F2_dfimm_p, {{ 0, false, 10, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_F2_sfclass, {{ 1, false, 5, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_F2_sfimm_n, {{ 0, false, 10, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_F2_sfimm_p, {{ 0, false, 10, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_M4_mpyri_addi, {{ 2, false, 6, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_M4_mpyri_addr_u2, {{ 1, false, 6, 2 }} },
- { Hexagon::BI__builtin_HEXAGON_S2_addasl_rrri, {{ 2, false, 3, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S2_asl_i_p_acc, {{ 2, false, 6, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S2_asl_i_p_and, {{ 2, false, 6, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S2_asl_i_p, {{ 1, false, 6, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S2_asl_i_p_nac, {{ 2, false, 6, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S2_asl_i_p_or, {{ 2, false, 6, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S2_asl_i_p_xacc, {{ 2, false, 6, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S2_asl_i_r_acc, {{ 2, false, 5, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S2_asl_i_r_and, {{ 2, false, 5, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S2_asl_i_r, {{ 1, false, 5, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S2_asl_i_r_nac, {{ 2, false, 5, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S2_asl_i_r_or, {{ 2, false, 5, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S2_asl_i_r_sat, {{ 1, false, 5, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S2_asl_i_r_xacc, {{ 2, false, 5, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S2_asl_i_vh, {{ 1, false, 4, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S2_asl_i_vw, {{ 1, false, 5, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S2_asr_i_p_acc, {{ 2, false, 6, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S2_asr_i_p_and, {{ 2, false, 6, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S2_asr_i_p, {{ 1, false, 6, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S2_asr_i_p_nac, {{ 2, false, 6, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S2_asr_i_p_or, {{ 2, false, 6, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S2_asr_i_p_rnd_goodsyntax,
- {{ 1, false, 6, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S2_asr_i_p_rnd, {{ 1, false, 6, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S2_asr_i_r_acc, {{ 2, false, 5, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S2_asr_i_r_and, {{ 2, false, 5, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S2_asr_i_r, {{ 1, false, 5, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S2_asr_i_r_nac, {{ 2, false, 5, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S2_asr_i_r_or, {{ 2, false, 5, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S2_asr_i_r_rnd_goodsyntax,
- {{ 1, false, 5, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S2_asr_i_r_rnd, {{ 1, false, 5, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S2_asr_i_svw_trun, {{ 1, false, 5, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S2_asr_i_vh, {{ 1, false, 4, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S2_asr_i_vw, {{ 1, false, 5, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S2_clrbit_i, {{ 1, false, 5, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S2_extractu, {{ 1, false, 5, 0 },
- { 2, false, 5, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S2_extractup, {{ 1, false, 6, 0 },
- { 2, false, 6, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S2_insert, {{ 2, false, 5, 0 },
- { 3, false, 5, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S2_insertp, {{ 2, false, 6, 0 },
- { 3, false, 6, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S2_lsr_i_p_acc, {{ 2, false, 6, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S2_lsr_i_p_and, {{ 2, false, 6, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S2_lsr_i_p, {{ 1, false, 6, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S2_lsr_i_p_nac, {{ 2, false, 6, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S2_lsr_i_p_or, {{ 2, false, 6, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S2_lsr_i_p_xacc, {{ 2, false, 6, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S2_lsr_i_r_acc, {{ 2, false, 5, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S2_lsr_i_r_and, {{ 2, false, 5, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S2_lsr_i_r, {{ 1, false, 5, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S2_lsr_i_r_nac, {{ 2, false, 5, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S2_lsr_i_r_or, {{ 2, false, 5, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S2_lsr_i_r_xacc, {{ 2, false, 5, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S2_lsr_i_vh, {{ 1, false, 4, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S2_lsr_i_vw, {{ 1, false, 5, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S2_setbit_i, {{ 1, false, 5, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S2_tableidxb_goodsyntax,
- {{ 2, false, 4, 0 },
- { 3, false, 5, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S2_tableidxd_goodsyntax,
- {{ 2, false, 4, 0 },
- { 3, false, 5, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S2_tableidxh_goodsyntax,
- {{ 2, false, 4, 0 },
- { 3, false, 5, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S2_tableidxw_goodsyntax,
- {{ 2, false, 4, 0 },
- { 3, false, 5, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S2_togglebit_i, {{ 1, false, 5, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S2_tstbit_i, {{ 1, false, 5, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S2_valignib, {{ 2, false, 3, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S2_vspliceib, {{ 2, false, 3, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S4_addi_asl_ri, {{ 2, false, 5, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S4_addi_lsr_ri, {{ 2, false, 5, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S4_andi_asl_ri, {{ 2, false, 5, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S4_andi_lsr_ri, {{ 2, false, 5, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S4_clbaddi, {{ 1, true , 6, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S4_clbpaddi, {{ 1, true, 6, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S4_extract, {{ 1, false, 5, 0 },
- { 2, false, 5, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S4_extractp, {{ 1, false, 6, 0 },
- { 2, false, 6, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S4_lsli, {{ 0, true, 6, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S4_ntstbit_i, {{ 1, false, 5, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S4_ori_asl_ri, {{ 2, false, 5, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S4_ori_lsr_ri, {{ 2, false, 5, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S4_subi_asl_ri, {{ 2, false, 5, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S4_subi_lsr_ri, {{ 2, false, 5, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S4_vrcrotate_acc, {{ 3, false, 2, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S4_vrcrotate, {{ 2, false, 2, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S5_asrhub_rnd_sat_goodsyntax,
- {{ 1, false, 4, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S5_asrhub_sat, {{ 1, false, 4, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S5_vasrhrnd_goodsyntax,
- {{ 1, false, 4, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S6_rol_i_p, {{ 1, false, 6, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S6_rol_i_p_acc, {{ 2, false, 6, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S6_rol_i_p_and, {{ 2, false, 6, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S6_rol_i_p_nac, {{ 2, false, 6, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S6_rol_i_p_or, {{ 2, false, 6, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S6_rol_i_p_xacc, {{ 2, false, 6, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S6_rol_i_r, {{ 1, false, 5, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S6_rol_i_r_acc, {{ 2, false, 5, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S6_rol_i_r_and, {{ 2, false, 5, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S6_rol_i_r_nac, {{ 2, false, 5, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S6_rol_i_r_or, {{ 2, false, 5, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_S6_rol_i_r_xacc, {{ 2, false, 5, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_V6_valignbi, {{ 2, false, 3, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_V6_valignbi_128B, {{ 2, false, 3, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_V6_vlalignbi, {{ 2, false, 3, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_V6_vlalignbi_128B, {{ 2, false, 3, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_V6_vrmpybusi, {{ 2, false, 1, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_V6_vrmpybusi_128B, {{ 2, false, 1, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_V6_vrmpybusi_acc, {{ 3, false, 1, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_V6_vrmpybusi_acc_128B,
- {{ 3, false, 1, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_V6_vrmpyubi, {{ 2, false, 1, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_V6_vrmpyubi_128B, {{ 2, false, 1, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_V6_vrmpyubi_acc, {{ 3, false, 1, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_V6_vrmpyubi_acc_128B,
- {{ 3, false, 1, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_V6_vrsadubi, {{ 2, false, 1, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_V6_vrsadubi_128B, {{ 2, false, 1, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_V6_vrsadubi_acc, {{ 3, false, 1, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_V6_vrsadubi_acc_128B,
- {{ 3, false, 1, 0 }} },
+ {Hexagon::BI__builtin_HEXAGON_A2_combineii, {{1, true, 8, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_A2_tfrih, {{1, false, 16, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_A2_tfril, {{1, false, 16, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_A2_tfrpi, {{0, true, 8, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_A4_bitspliti, {{1, false, 5, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_A4_cmpbeqi, {{1, false, 8, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_A4_cmpbgti, {{1, true, 8, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_A4_cround_ri, {{1, false, 5, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_A4_round_ri, {{1, false, 5, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_A4_round_ri_sat, {{1, false, 5, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_A4_vcmpbeqi, {{1, false, 8, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_A4_vcmpbgti, {{1, true, 8, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_A4_vcmpbgtui, {{1, false, 7, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_A4_vcmpheqi, {{1, true, 8, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_A4_vcmphgti, {{1, true, 8, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_A4_vcmphgtui, {{1, false, 7, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_A4_vcmpweqi, {{1, true, 8, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_A4_vcmpwgti, {{1, true, 8, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_A4_vcmpwgtui, {{1, false, 7, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_C2_bitsclri, {{1, false, 6, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_C2_muxii, {{2, true, 8, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_C4_nbitsclri, {{1, false, 6, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_F2_dfclass, {{1, false, 5, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_F2_dfimm_n, {{0, false, 10, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_F2_dfimm_p, {{0, false, 10, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_F2_sfclass, {{1, false, 5, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_F2_sfimm_n, {{0, false, 10, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_F2_sfimm_p, {{0, false, 10, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_M4_mpyri_addi, {{2, false, 6, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_M4_mpyri_addr_u2, {{1, false, 6, 2}}},
+ {Hexagon::BI__builtin_HEXAGON_S2_addasl_rrri, {{2, false, 3, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S2_asl_i_p_acc, {{2, false, 6, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S2_asl_i_p_and, {{2, false, 6, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S2_asl_i_p, {{1, false, 6, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S2_asl_i_p_nac, {{2, false, 6, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S2_asl_i_p_or, {{2, false, 6, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S2_asl_i_p_xacc, {{2, false, 6, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S2_asl_i_r_acc, {{2, false, 5, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S2_asl_i_r_and, {{2, false, 5, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S2_asl_i_r, {{1, false, 5, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S2_asl_i_r_nac, {{2, false, 5, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S2_asl_i_r_or, {{2, false, 5, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S2_asl_i_r_sat, {{1, false, 5, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S2_asl_i_r_xacc, {{2, false, 5, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S2_asl_i_vh, {{1, false, 4, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S2_asl_i_vw, {{1, false, 5, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S2_asr_i_p_acc, {{2, false, 6, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S2_asr_i_p_and, {{2, false, 6, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S2_asr_i_p, {{1, false, 6, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S2_asr_i_p_nac, {{2, false, 6, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S2_asr_i_p_or, {{2, false, 6, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S2_asr_i_p_rnd_goodsyntax,
+ {{1, false, 6, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S2_asr_i_p_rnd, {{1, false, 6, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S2_asr_i_r_acc, {{2, false, 5, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S2_asr_i_r_and, {{2, false, 5, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S2_asr_i_r, {{1, false, 5, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S2_asr_i_r_nac, {{2, false, 5, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S2_asr_i_r_or, {{2, false, 5, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S2_asr_i_r_rnd_goodsyntax,
+ {{1, false, 5, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S2_asr_i_r_rnd, {{1, false, 5, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S2_asr_i_svw_trun, {{1, false, 5, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S2_asr_i_vh, {{1, false, 4, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S2_asr_i_vw, {{1, false, 5, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S2_clrbit_i, {{1, false, 5, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S2_extractu,
+ {{1, false, 5, 0}, {2, false, 5, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S2_extractup,
+ {{1, false, 6, 0}, {2, false, 6, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S2_insert,
+ {{2, false, 5, 0}, {3, false, 5, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S2_insertp,
+ {{2, false, 6, 0}, {3, false, 6, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S2_lsr_i_p_acc, {{2, false, 6, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S2_lsr_i_p_and, {{2, false, 6, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S2_lsr_i_p, {{1, false, 6, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S2_lsr_i_p_nac, {{2, false, 6, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S2_lsr_i_p_or, {{2, false, 6, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S2_lsr_i_p_xacc, {{2, false, 6, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S2_lsr_i_r_acc, {{2, false, 5, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S2_lsr_i_r_and, {{2, false, 5, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S2_lsr_i_r, {{1, false, 5, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S2_lsr_i_r_nac, {{2, false, 5, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S2_lsr_i_r_or, {{2, false, 5, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S2_lsr_i_r_xacc, {{2, false, 5, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S2_lsr_i_vh, {{1, false, 4, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S2_lsr_i_vw, {{1, false, 5, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S2_setbit_i, {{1, false, 5, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S2_tableidxb_goodsyntax,
+ {{2, false, 4, 0}, {3, false, 5, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S2_tableidxd_goodsyntax,
+ {{2, false, 4, 0}, {3, false, 5, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S2_tableidxh_goodsyntax,
+ {{2, false, 4, 0}, {3, false, 5, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S2_tableidxw_goodsyntax,
+ {{2, false, 4, 0}, {3, false, 5, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S2_togglebit_i, {{1, false, 5, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S2_tstbit_i, {{1, false, 5, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S2_valignib, {{2, false, 3, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S2_vspliceib, {{2, false, 3, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S4_addi_asl_ri, {{2, false, 5, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S4_addi_lsr_ri, {{2, false, 5, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S4_andi_asl_ri, {{2, false, 5, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S4_andi_lsr_ri, {{2, false, 5, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S4_clbaddi, {{1, true, 6, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S4_clbpaddi, {{1, true, 6, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S4_extract,
+ {{1, false, 5, 0}, {2, false, 5, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S4_extractp,
+ {{1, false, 6, 0}, {2, false, 6, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S4_lsli, {{0, true, 6, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S4_ntstbit_i, {{1, false, 5, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S4_ori_asl_ri, {{2, false, 5, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S4_ori_lsr_ri, {{2, false, 5, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S4_subi_asl_ri, {{2, false, 5, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S4_subi_lsr_ri, {{2, false, 5, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S4_vrcrotate_acc, {{3, false, 2, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S4_vrcrotate, {{2, false, 2, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S5_asrhub_rnd_sat_goodsyntax,
+ {{1, false, 4, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S5_asrhub_sat, {{1, false, 4, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S5_vasrhrnd_goodsyntax, {{1, false, 4, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S6_rol_i_p, {{1, false, 6, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S6_rol_i_p_acc, {{2, false, 6, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S6_rol_i_p_and, {{2, false, 6, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S6_rol_i_p_nac, {{2, false, 6, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S6_rol_i_p_or, {{2, false, 6, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S6_rol_i_p_xacc, {{2, false, 6, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S6_rol_i_r, {{1, false, 5, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S6_rol_i_r_acc, {{2, false, 5, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S6_rol_i_r_and, {{2, false, 5, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S6_rol_i_r_nac, {{2, false, 5, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S6_rol_i_r_or, {{2, false, 5, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_S6_rol_i_r_xacc, {{2, false, 5, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_V6_valignbi, {{2, false, 3, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_V6_valignbi_128B, {{2, false, 3, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_V6_vlalignbi, {{2, false, 3, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_V6_vlalignbi_128B, {{2, false, 3, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_V6_vrmpybusi, {{2, false, 1, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_V6_vrmpybusi_128B, {{2, false, 1, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_V6_vrmpybusi_acc, {{3, false, 1, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_V6_vrmpybusi_acc_128B, {{3, false, 1, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_V6_vrmpyubi, {{2, false, 1, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_V6_vrmpyubi_128B, {{2, false, 1, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_V6_vrmpyubi_acc, {{3, false, 1, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_V6_vrmpyubi_acc_128B, {{3, false, 1, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_V6_vrsadubi, {{2, false, 1, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_V6_vrsadubi_128B, {{2, false, 1, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_V6_vrsadubi_acc, {{3, false, 1, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_V6_vrsadubi_acc_128B, {{3, false, 1, 0}}},
- { Hexagon::BI__builtin_HEXAGON_V6_v6mpyhubs10, {{ 2, false, 2, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_V6_v6mpyhubs10_128B,
- {{ 2, false, 2, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_V6_v6mpyhubs10_vxx,
- {{ 3, false, 2, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_V6_v6mpyhubs10_vxx_128B,
- {{ 3, false, 2, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_V6_v6mpyvubs10, {{ 2, false, 2, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_V6_v6mpyvubs10_128B,
- {{ 2, false, 2, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_V6_v6mpyvubs10_vxx,
- {{ 3, false, 2, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_V6_v6mpyvubs10_vxx_128B,
- {{ 3, false, 2, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_V6_vlutvvbi, {{ 2, false, 3, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_V6_vlutvvbi_128B, {{ 2, false, 3, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_V6_vlutvvb_oracci, {{ 3, false, 3, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_V6_vlutvvb_oracci_128B,
- {{ 3, false, 3, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_V6_vlutvwhi, {{ 2, false, 3, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_V6_vlutvwhi_128B, {{ 2, false, 3, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_V6_vlutvwh_oracci, {{ 3, false, 3, 0 }} },
- { Hexagon::BI__builtin_HEXAGON_V6_vlutvwh_oracci_128B,
- {{ 3, false, 3, 0 }} },
+ {Hexagon::BI__builtin_HEXAGON_V6_v6mpyhubs10, {{2, false, 2, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_V6_v6mpyhubs10_128B, {{2, false, 2, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_V6_v6mpyhubs10_vxx, {{3, false, 2, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_V6_v6mpyhubs10_vxx_128B,
+ {{3, false, 2, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_V6_v6mpyvubs10, {{2, false, 2, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_V6_v6mpyvubs10_128B, {{2, false, 2, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_V6_v6mpyvubs10_vxx, {{3, false, 2, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_V6_v6mpyvubs10_vxx_128B,
+ {{3, false, 2, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_V6_vlutvvbi, {{2, false, 3, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_V6_vlutvvbi_128B, {{2, false, 3, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_V6_vlutvvb_oracci, {{3, false, 3, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_V6_vlutvvb_oracci_128B, {{3, false, 3, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_V6_vlutvwhi, {{2, false, 3, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_V6_vlutvwhi_128B, {{2, false, 3, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_V6_vlutvwh_oracci, {{3, false, 3, 0}}},
+ {Hexagon::BI__builtin_HEXAGON_V6_vlutvwh_oracci_128B, {{3, false, 3, 0}}},
};
// Use a dynamically initialized static to sort the table exactly once on
diff --git a/clang/lib/Sema/SemaMIPS.cpp b/clang/lib/Sema/SemaMIPS.cpp
index df5328fbf6..fc4768ec3f 100644
--- a/clang/lib/Sema/SemaMIPS.cpp
+++ b/clang/lib/Sema/SemaMIPS.cpp
@@ -63,14 +63,43 @@ bool SemaMIPS::CheckMipsBuiltinCpu(const TargetInfo &TI, unsigned BuiltinID,
bool SemaMIPS::CheckMipsBuiltinArgument(unsigned BuiltinID, CallExpr *TheCall) {
unsigned i = 0, l = 0, u = 0, m = 0;
switch (BuiltinID) {
- default: return false;
- case Mips::BI__builtin_mips_wrdsp: i = 1; l = 0; u = 63; break;
- case Mips::BI__builtin_mips_rddsp: i = 0; l = 0; u = 63; break;
- case Mips::BI__builtin_mips_append: i = 2; l = 0; u = 31; break;
- case Mips::BI__builtin_mips_balign: i = 2; l = 0; u = 3; break;
- case Mips::BI__builtin_mips_precr_sra_ph_w: i = 2; l = 0; u = 31; break;
- case Mips::BI__builtin_mips_precr_sra_r_ph_w: i = 2; l = 0; u = 31; break;
- case Mips::BI__builtin_mips_prepend: i = 2; l = 0; u = 31; break;
+ default:
+ return false;
+ case Mips::BI__builtin_mips_wrdsp:
+ i = 1;
+ l = 0;
+ u = 63;
+ break;
+ case Mips::BI__builtin_mips_rddsp:
+ i = 0;
+ l = 0;
+ u = 63;
+ break;
+ case Mips::BI__builtin_mips_append:
+ i = 2;
+ l = 0;
+ u = 31;
+ break;
+ case Mips::BI__builtin_mips_balign:
+ i = 2;
+ l = 0;
+ u = 3;
+ break;
+ case Mips::BI__builtin_mips_precr_sra_ph_w:
+ i = 2;
+ l = 0;
+ u = 31;
+ break;
+ case Mips::BI__builtin_mips_precr_sra_r_ph_w:
+ i = 2;
+ l = 0;
+ u = 31;
+ break;
+ case Mips::BI__builtin_mips_prepend:
+ i = 2;
+ l = 0;
+ u = 31;
+ break;
// MSA intrinsics. Instructions (which the intrinsics maps to) which use the
// df/m field.
// These intrinsics take an unsigned 3 bit immediate.
@@ -83,9 +112,17 @@ bool SemaMIPS::CheckMipsBuiltinArgument(unsigned BuiltinID, CallExpr *TheCall) {
case Mips::BI__builtin_msa_srai_b:
case Mips::BI__builtin_msa_srari_b:
case Mips::BI__builtin_msa_srli_b:
- case Mips::BI__builtin_msa_srlri_b: i = 1; l = 0; u = 7; break;
+ case Mips::BI__builtin_msa_srlri_b:
+ i = 1;
+ l = 0;
+ u = 7;
+ break;
case Mips::BI__builtin_msa_binsli_b:
- case Mips::BI__builtin_msa_binsri_b: i = 2; l = 0; u = 7; break;
+ case Mips::BI__builtin_msa_binsri_b:
+ i = 2;
+ l = 0;
+ u = 7;
+ break;
// These intrinsics take an unsigned 4 bit immediate.
case Mips::BI__builtin_msa_bclri_h:
case Mips::BI__builtin_msa_bnegi_h:
@@ -96,14 +133,26 @@ bool SemaMIPS::CheckMipsBuiltinArgument(unsigned BuiltinID, CallExpr *TheCall) {
case Mips::BI__builtin_msa_srai_h:
case Mips::BI__builtin_msa_srari_h:
case Mips::BI__builtin_msa_srli_h:
- case Mips::BI__builtin_msa_srlri_h: i = 1; l = 0; u = 15; break;
+ case Mips::BI__builtin_msa_srlri_h:
+ i = 1;
+ l = 0;
+ u = 15;
+ break;
case Mips::BI__builtin_msa_binsli_h:
- case Mips::BI__builtin_msa_binsri_h: i = 2; l = 0; u = 15; break;
+ case Mips::BI__builtin_msa_binsri_h:
+ i = 2;
+ l = 0;
+ u = 15;
+ break;
// These intrinsics take an unsigned 5 bit immediate.
// The first block of intrinsics actually have an unsigned 5 bit field,
// not a df/n field.
case Mips::BI__builtin_msa_cfcmsa:
- case Mips::BI__builtin_msa_ctcmsa: i = 0; l = 0; u = 31; break;
+ case Mips::BI__builtin_msa_ctcmsa:
+ i = 0;
+ l = 0;
+ u = 31;
+ break;
case Mips::BI__builtin_msa_clei_u_b:
case Mips::BI__builtin_msa_clei_u_h:
case Mips::BI__builtin_msa_clei_u_w:
@@ -137,9 +186,17 @@ bool SemaMIPS::CheckMipsBuiltinArgument(unsigned BuiltinID, CallExpr *TheCall) {
case Mips::BI__builtin_msa_subvi_b:
case Mips::BI__builtin_msa_subvi_h:
case Mips::BI__builtin_msa_subvi_w:
- case Mips::BI__builtin_msa_subvi_d: i = 1; l = 0; u = 31; break;
+ case Mips::BI__builtin_msa_subvi_d:
+ i = 1;
+ l = 0;
+ u = 31;
+ break;
case Mips::BI__builtin_msa_binsli_w:
- case Mips::BI__builtin_msa_binsri_w: i = 2; l = 0; u = 31; break;
+ case Mips::BI__builtin_msa_binsri_w:
+ i = 2;
+ l = 0;
+ u = 31;
+ break;
// These intrinsics take an unsigned 6 bit immediate.
case Mips::BI__builtin_msa_bclri_d:
case Mips::BI__builtin_msa_bnegi_d:
@@ -150,9 +207,17 @@ bool SemaMIPS::CheckMipsBuiltinArgument(unsigned BuiltinID, CallExpr *TheCall) {
case Mips::BI__builtin_msa_srai_d:
case Mips::BI__builtin_msa_srari_d:
case Mips::BI__builtin_msa_srli_d:
- case Mips::BI__builtin_msa_srlri_d: i = 1; l = 0; u = 63; break;
+ case Mips::BI__builtin_msa_srlri_d:
+ i = 1;
+ l = 0;
+ u = 63;
+ break;
case Mips::BI__builtin_msa_binsli_d:
- case Mips::BI__builtin_msa_binsri_d: i = 2; l = 0; u = 63; break;
+ case Mips::BI__builtin_msa_binsri_d:
+ i = 2;
+ l = 0;
+ u = 63;
+ break;
// These intrinsics take a signed 5 bit immediate.
case Mips::BI__builtin_msa_ceqi_b:
case Mips::BI__builtin_msa_ceqi_h:
@@ -173,7 +238,11 @@ bool SemaMIPS::CheckMipsBuiltinArgument(unsigned BuiltinID, CallExpr *TheCall) {
case Mips::BI__builtin_msa_mini_s_b:
case Mips::BI__builtin_msa_mini_s_h:
case Mips::BI__builtin_msa_mini_s_w:
- case Mips::BI__builtin_msa_mini_s_d: i = 1; l = -16; u = 15; break;
+ case Mips::BI__builtin_msa_mini_s_d:
+ i = 1;
+ l = -16;
+ u = 15;
+ break;
// These intrinsics take an unsigned 8 bit immediate.
case Mips::BI__builtin_msa_andi_b:
case Mips::BI__builtin_msa_nori_b:
@@ -181,53 +250,161 @@ bool SemaMIPS::CheckMipsBuiltinArgument(unsigned BuiltinID, CallExpr *TheCall) {
case Mips::BI__builtin_msa_shf_b:
case Mips::BI__builtin_msa_shf_h:
case Mips::BI__builtin_msa_shf_w:
- case Mips::BI__builtin_msa_xori_b: i = 1; l = 0; u = 255; break;
+ case Mips::BI__builtin_msa_xori_b:
+ i = 1;
+ l = 0;
+ u = 255;
+ break;
case Mips::BI__builtin_msa_bseli_b:
case Mips::BI__builtin_msa_bmnzi_b:
- case Mips::BI__builtin_msa_bmzi_b: i = 2; l = 0; u = 255; break;
+ case Mips::BI__builtin_msa_bmzi_b:
+ i = 2;
+ l = 0;
+ u = 255;
+ break;
// df/n format
// These intrinsics take an unsigned 4 bit immediate.
case Mips::BI__builtin_msa_copy_s_b:
case Mips::BI__builtin_msa_copy_u_b:
case Mips::BI__builtin_msa_insve_b:
- case Mips::BI__builtin_msa_splati_b: i = 1; l = 0; u = 15; break;
- case Mips::BI__builtin_msa_sldi_b: i = 2; l = 0; u = 15; break;
+ case Mips::BI__builtin_msa_splati_b:
+ i = 1;
+ l = 0;
+ u = 15;
+ break;
+ case Mips::BI__builtin_msa_sldi_b:
+ i = 2;
+ l = 0;
+ u = 15;
+ break;
// These intrinsics take an unsigned 3 bit immediate.
case Mips::BI__builtin_msa_copy_s_h:
case Mips::BI__builtin_msa_copy_u_h:
case Mips::BI__builtin_msa_insve_h:
- case Mips::BI__builtin_msa_splati_h: i = 1; l = 0; u = 7; break;
- case Mips::BI__builtin_msa_sldi_h: i = 2; l = 0; u = 7; break;
+ case Mips::BI__builtin_msa_splati_h:
+ i = 1;
+ l = 0;
+ u = 7;
+ break;
+ case Mips::BI__builtin_msa_sldi_h:
+ i = 2;
+ l = 0;
+ u = 7;
+ break;
// These intrinsics take an unsigned 2 bit immediate.
case Mips::BI__builtin_msa_copy_s_w:
case Mips::BI__builtin_msa_copy_u_w:
case Mips::BI__builtin_msa_insve_w:
- case Mips::BI__builtin_msa_splati_w: i = 1; l = 0; u = 3; break;
- case Mips::BI__builtin_msa_sldi_w: i = 2; l = 0; u = 3; break;
+ case Mips::BI__builtin_msa_splati_w:
+ i = 1;
+ l = 0;
+ u = 3;
+ break;
+ case Mips::BI__builtin_msa_sldi_w:
+ i = 2;
+ l = 0;
+ u = 3;
+ break;
// These intrinsics take an unsigned 1 bit immediate.
case Mips::BI__builtin_msa_copy_s_d:
case Mips::BI__builtin_msa_copy_u_d:
case Mips::BI__builtin_msa_insve_d:
- case Mips::BI__builtin_msa_splati_d: i = 1; l = 0; u = 1; break;
- case Mips::BI__builtin_msa_sldi_d: i = 2; l = 0; u = 1; break;
+ case Mips::BI__builtin_msa_splati_d:
+ i = 1;
+ l = 0;
+ u = 1;
+ break;
+ case Mips::BI__builtin_msa_sldi_d:
+ i = 2;
+ l = 0;
+ u = 1;
+ break;
// Memory offsets and immediate loads.
// These intrinsics take a signed 10 bit immediate.
- case Mips::BI__builtin_msa_ldi_b: i = 0; l = -128; u = 255; break;
+ case Mips::BI__builtin_msa_ldi_b:
+ i = 0;
+ l = -128;
+ u = 255;
+ break;
case Mips::BI__builtin_msa_ldi_h:
case Mips::BI__builtin_msa_ldi_w:
- case Mips::BI__builtin_msa_ldi_d: i = 0; l = -512; u = 511; break;
- case Mips::BI__builtin_msa_ld_b: i = 1; l = -512; u = 511; m = 1; break;
- case Mips::BI__builtin_msa_ld_h: i = 1; l = -1024; u = 1022; m = 2; break;
- case Mips::BI__builtin_msa_ld_w: i = 1; l = -2048; u = 2044; m = 4; break;
- case Mips::BI__builtin_msa_ld_d: i = 1; l = -4096; u = 4088; m = 8; break;
- case Mips::BI__builtin_msa_ldr_d: i = 1; l = -4096; u = 4088; m = 8; break;
- case Mips::BI__builtin_msa_ldr_w: i = 1; l = -2048; u = 2044; m = 4; break;
- case Mips::BI__builtin_msa_st_b: i = 2; l = -512; u = 511; m = 1; break;
- case Mips::BI__builtin_msa_st_h: i = 2; l = -1024; u = 1022; m = 2; break;
- case Mips::BI__builtin_msa_st_w: i = 2; l = -2048; u = 2044; m = 4; break;
- case Mips::BI__builtin_msa_st_d: i = 2; l = -4096; u = 4088; m = 8; break;
- case Mips::BI__builtin_msa_str_d: i = 2; l = -4096; u = 4088; m = 8; break;
- case Mips::BI__builtin_msa_str_w: i = 2; l = -2048; u = 2044; m = 4; break;
+ case Mips::BI__builtin_msa_ldi_d:
+ i = 0;
+ l = -512;
+ u = 511;
+ break;
+ case Mips::BI__builtin_msa_ld_b:
+ i = 1;
+ l = -512;
+ u = 511;
+ m = 1;
+ break;
+ case Mips::BI__builtin_msa_ld_h:
+ i = 1;
+ l = -1024;
+ u = 1022;
+ m = 2;
+ break;
+ case Mips::BI__builtin_msa_ld_w:
+ i = 1;
+ l = -2048;
+ u = 2044;
+ m = 4;
+ break;
+ case Mips::BI__builtin_msa_ld_d:
+ i = 1;
+ l = -4096;
+ u = 4088;
+ m = 8;
+ break;
+ case Mips::BI__builtin_msa_ldr_d:
+ i = 1;
+ l = -4096;
+ u = 4088;
+ m = 8;
+ break;
+ case Mips::BI__builtin_msa_ldr_w:
+ i = 1;
+ l = -2048;
+ u = 2044;
+ m = 4;
+ break;
+ case Mips::BI__builtin_msa_st_b:
+ i = 2;
+ l = -512;
+ u = 511;
+ m = 1;
+ break;
+ case Mips::BI__builtin_msa_st_h:
+ i = 2;
+ l = -1024;
+ u = 1022;
+ m = 2;
+ break;
+ case Mips::BI__builtin_msa_st_w:
+ i = 2;
+ l = -2048;
+ u = 2044;
+ m = 4;
+ break;
+ case Mips::BI__builtin_msa_st_d:
+ i = 2;
+ l = -4096;
+ u = 4088;
+ m = 8;
+ break;
+ case Mips::BI__builtin_msa_str_d:
+ i = 2;
+ l = -4096;
+ u = 4088;
+ m = 8;
+ break;
+ case Mips::BI__builtin_msa_str_w:
+ i = 2;
+ l = -2048;
+ u = 2044;
+ m = 4;
+ break;
}
if (!m)
diff --git a/clang/lib/Sema/SemaSystemZ.cpp b/clang/lib/Sema/SemaSystemZ.cpp
index 7e836adbee..e6e4e3dc59 100644
--- a/clang/lib/Sema/SemaSystemZ.cpp
+++ b/clang/lib/Sema/SemaSystemZ.cpp
@@ -36,12 +36,21 @@ bool SemaSystemZ::CheckSystemZBuiltinFunctionCall(unsigned BuiltinID,
// range check them here.
unsigned i = 0, l = 0, u = 0;
switch (BuiltinID) {
- default: return false;
- case SystemZ::BI__builtin_s390_lcbb: i = 1; l = 0; u = 15; break;
+ default:
+ return false;
+ case SystemZ::BI__builtin_s390_lcbb:
+ i = 1;
+ l = 0;
+ u = 15;
+ break;
case SystemZ::BI__builtin_s390_verimb:
case SystemZ::BI__builtin_s390_verimh:
case SystemZ::BI__builtin_s390_verimf:
- case SystemZ::BI__builtin_s390_verimg: i = 3; l = 0; u = 255; break;
+ case SystemZ::BI__builtin_s390_verimg:
+ i = 3;
+ l = 0;
+ u = 255;
+ break;
case SystemZ::BI__builtin_s390_vfaeb:
case SystemZ::BI__builtin_s390_vfaeh:
case SystemZ::BI__builtin_s390_vfaef:
@@ -53,16 +62,36 @@ bool SemaSystemZ::CheckSystemZBuiltinFunctionCall(unsigned BuiltinID,
case SystemZ::BI__builtin_s390_vfaezf:
case SystemZ::BI__builtin_s390_vfaezbs:
case SystemZ::BI__builtin_s390_vfaezhs:
- case SystemZ::BI__builtin_s390_vfaezfs: i = 2; l = 0; u = 15; break;
+ case SystemZ::BI__builtin_s390_vfaezfs:
+ i = 2;
+ l = 0;
+ u = 15;
+ break;
case SystemZ::BI__builtin_s390_vfisb:
case SystemZ::BI__builtin_s390_vfidb:
return SemaRef.BuiltinConstantArgRange(TheCall, 1, 0, 15) ||
SemaRef.BuiltinConstantArgRange(TheCall, 2, 0, 15);
case SystemZ::BI__builtin_s390_vftcisb:
- case SystemZ::BI__builtin_s390_vftcidb: i = 1; l = 0; u = 4095; break;
- case SystemZ::BI__builtin_s390_vlbb: i = 1; l = 0; u = 15; break;
- case SystemZ::BI__builtin_s390_vpdi: i = 2; l = 0; u = 15; break;
- case SystemZ::BI__builtin_s390_vsldb: i = 2; l = 0; u = 15; break;
+ case SystemZ::BI__builtin_s390_vftcidb:
+ i = 1;
+ l = 0;
+ u = 4095;
+ break;
+ case SystemZ::BI__builtin_s390_vlbb:
+ i = 1;
+ l = 0;
+ u = 15;
+ break;
+ case SystemZ::BI__builtin_s390_vpdi:
+ i = 2;
+ l = 0;
+ u = 15;
+ break;
+ case SystemZ::BI__builtin_s390_vsldb:
+ i = 2;
+ l = 0;
+ u = 15;
+ break;
case SystemZ::BI__builtin_s390_vstrcb:
case SystemZ::BI__builtin_s390_vstrch:
case SystemZ::BI__builtin_s390_vstrcf:
@@ -74,19 +103,47 @@ bool SemaSystemZ::CheckSystemZBuiltinFunctionCall(unsigned BuiltinID,
case SystemZ::BI__builtin_s390_vstrcfs:
case SystemZ::BI__builtin_s390_vstrczbs:
case SystemZ::BI__builtin_s390_vstrczhs:
- case SystemZ::BI__builtin_s390_vstrczfs: i = 3; l = 0; u = 15; break;
- case SystemZ::BI__builtin_s390_vmslg: i = 3; l = 0; u = 15; break;
+ case SystemZ::BI__builtin_s390_vstrczfs:
+ i = 3;
+ l = 0;
+ u = 15;
+ break;
+ case SystemZ::BI__builtin_s390_vmslg:
+ i = 3;
+ l = 0;
+ u = 15;
+ break;
case SystemZ::BI__builtin_s390_vfminsb:
case SystemZ::BI__builtin_s390_vfmaxsb:
case SystemZ::BI__builtin_s390_vfmindb:
- case SystemZ::BI__builtin_s390_vfmaxdb: i = 2; l = 0; u = 15; break;
- case SystemZ::BI__builtin_s390_vsld: i = 2; l = 0; u = 7; break;
- case SystemZ::BI__builtin_s390_vsrd: i = 2; l = 0; u = 7; break;
+ case SystemZ::BI__builtin_s390_vfmaxdb:
+ i = 2;
+ l = 0;
+ u = 15;
+ break;
+ case SystemZ::BI__builtin_s390_vsld:
+ i = 2;
+ l = 0;
+ u = 7;
+ break;
+ case SystemZ::BI__builtin_s390_vsrd:
+ i = 2;
+ l = 0;
+ u = 7;
+ break;
case SystemZ::BI__builtin_s390_vclfnhs:
case SystemZ::BI__builtin_s390_vclfnls:
case SystemZ::BI__builtin_s390_vcfn:
- case SystemZ::BI__builtin_s390_vcnf: i = 1; l = 0; u = 15; break;
- case SystemZ::BI__builtin_s390_vcrnfs: i = 2; l = 0; u = 15; break;
+ case SystemZ::BI__builtin_s390_vcnf:
+ i = 1;
+ l = 0;
+ u = 15;
+ break;
+ case SystemZ::BI__builtin_s390_vcrnfs:
+ i = 2;
+ l = 0;
+ u = 15;
+ break;
}
return SemaRef.BuiltinConstantArgRange(TheCall, i, l, u);
}
|
Endilll
requested review from
uweigand,
arsenm,
jholewinski,
TNorthover and
chenzheng1030
|
The only thing clang-format complain about is switches over built-ins for ARM, Hexagon, MIPS, and SystemZ. I don't feel like it makes improvements there, but open for input from contributors in those areas. |
arsenm
reviewed
May 23, 2024
AMDGPU has been already caught, I updated the rest. Thank you! |
erichkeane
reviewed
May 23, 2024
erichkeane
approved these changes
May 23, 2024
SixWeining
approved these changes
May 24, 2024
uweigand
reviewed
May 24, 2024
cor3ntin
reviewed
May 29, 2024
|
These Sema refactorings have been increasing the time to build clang by a small increment with every patch -- this one is an extra large jump of 0.7% (https://llvm-compile-time-tracker.com/compare.php?from=59e2a6b08f3e40afea87da3838ba69e1e15b6672&to=8aa80199751b0cd6631d057b0bfb21584acb206f&stat=instructions:u). |
|
Thank you for letting me know! Given the amount of positive feedback I've heard about this effort, I think we'll continue, trying to claw back the compile times elsewhere (my recent patch that removed try_compile checks from CMake should've helped, even if it's not counted in your metrics). |
|
Mildly curious that there isn't a SemaX86? Doh, there already is one. Don't mind me. |
This PR was based on the success with X86 and RISCV. |
|
I wonder if compile-time regressions come from new translation units I add, because they definitely include stuff. |
Yes, I believe that is the primary contributor. You can see the per-file breakdown here: https://llvm-compile-time-tracker.com/compare_clang.php?from=59e2a6b08f3e40afea87da3838ba69e1e15b6672&to=8aa80199751b0cd6631d057b0bfb21584acb206f&stat=instructions%3Au&sortBy=absolute-difference |
Endilll
added a commit
that referenced
this pull request
Jun 5, 2024
This patch moves language- and target-specific functions out of `SemaDeclAttr.cpp`. As a consequence, `SemaAVR`, `SemaM68k`, `SemaMSP430`, `SemaOpenCL`, `SemaSwift` were created (but they are not the only languages and targets affected). Notable things are that `Sema.h` actually grew a bit, because of templated helpers that rely on `Sema` that I had to make available from outside of `SemaDeclAttr.cpp`. I also had to left CUDA-related in `SemaDeclAttr.cpp`, because it looks like HIP is building up on top of CUDA attributes. This is a follow-up to #93179 and continuation of efforts to split `Sema` up. Additional context can be found in #84184 and #92682.
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This patch introduces
SemaAMDGPU,SemaARM,SemaBPF,SemaHexagon,SemaLoongArch,SemaMIPS,SemaNVPTX,SemaPPC,SemaSystemZ,SemaWasm. This continues previous efforts to split Sema up. Additional context can be found in #84184 and #92682.I decided to bundle target-specific components together because of their low impact on
Sema. That said, their impact onSemaChecking.cppis far from low, and I consider it a success.Somewhat accidentally, I also moved Wasm- and AMDGPU-specific function from
SemaDeclAttr.cpp, because they were exposed inSema. That went well, and I consider it a success, too. I'd like to move the rest of static target-specific functions out ofSemaDeclAttr.cpplike we're doing with built-ins inSemaChecking.cpp.