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[DAGCombiner] Push freeze through SETCC and SELECT_CC #94492

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Merged
merged 1 commit into from
Jul 22, 2024
Merged

[DAGCombiner] Push freeze through SETCC and SELECT_CC #94492

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2 changes: 2 additions & 0 deletions llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -15653,6 +15653,8 @@ SDValue DAGCombiner::visitFREEZE(SDNode *N) {
return SDValue();

bool AllowMultipleMaybePoisonOperands =
N0.getOpcode() == ISD::SELECT_CC ||
N0.getOpcode() == ISD::SETCC ||
N0.getOpcode() == ISD::BUILD_VECTOR ||
N0.getOpcode() == ISD::BUILD_PAIR ||
N0.getOpcode() == ISD::VECTOR_SHUFFLE ||
Expand Down
3 changes: 1 addition & 2 deletions llvm/test/CodeGen/RISCV/double-convert.ll
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Expand Up @@ -742,9 +742,8 @@ define i64 @fcvt_l_d_sat(double %a) nounwind {
; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI12_0)(a2)
; RV32IZFINXZDINX-NEXT: fle.d a2, a2, s0
; RV32IZFINXZDINX-NEXT: lui a5, 524288
; RV32IZFINXZDINX-NEXT: li a4, 1
; RV32IZFINXZDINX-NEXT: lui a3, 524288
; RV32IZFINXZDINX-NEXT: bne a2, a4, .LBB12_2
; RV32IZFINXZDINX-NEXT: beqz a2, .LBB12_2
; RV32IZFINXZDINX-NEXT: # %bb.1: # %start
; RV32IZFINXZDINX-NEXT: mv a3, a1
; RV32IZFINXZDINX-NEXT: .LBB12_2: # %start
Expand Down
174 changes: 84 additions & 90 deletions llvm/test/CodeGen/RISCV/double-round-conv-sat.ll
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Expand Up @@ -102,30 +102,29 @@ define i64 @test_floor_si64(double %x) nounwind {
; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI1_0)
; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI1_0+4)(a2)
; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI1_0)(a2)
; RV32IZFINXZDINX-NEXT: fle.d a2, a2, s0
; RV32IZFINXZDINX-NEXT: lui a4, %hi(.LCPI1_1)
; RV32IZFINXZDINX-NEXT: lw a5, %lo(.LCPI1_1+4)(a4)
; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI1_1)(a4)
; RV32IZFINXZDINX-NEXT: fle.d a6, a2, s0
; RV32IZFINXZDINX-NEXT: neg a2, a6
; RV32IZFINXZDINX-NEXT: and a0, a2, a0
; RV32IZFINXZDINX-NEXT: flt.d a4, a4, s0
; RV32IZFINXZDINX-NEXT: neg a2, a4
; RV32IZFINXZDINX-NEXT: or a0, a2, a0
; RV32IZFINXZDINX-NEXT: feq.d a2, s0, s0
; RV32IZFINXZDINX-NEXT: neg a2, a2
; RV32IZFINXZDINX-NEXT: lui a5, 524288
; RV32IZFINXZDINX-NEXT: li a4, 1
; RV32IZFINXZDINX-NEXT: lui a3, 524288
; RV32IZFINXZDINX-NEXT: bne a2, a4, .LBB1_2
; RV32IZFINXZDINX-NEXT: beqz a6, .LBB1_2
; RV32IZFINXZDINX-NEXT: # %bb.1:
; RV32IZFINXZDINX-NEXT: mv a3, a1
; RV32IZFINXZDINX-NEXT: .LBB1_2:
; RV32IZFINXZDINX-NEXT: lui a1, %hi(.LCPI1_1)
; RV32IZFINXZDINX-NEXT: lw a6, %lo(.LCPI1_1)(a1)
; RV32IZFINXZDINX-NEXT: lw a7, %lo(.LCPI1_1+4)(a1)
; RV32IZFINXZDINX-NEXT: flt.d a4, a6, s0
; RV32IZFINXZDINX-NEXT: and a0, a2, a0
; RV32IZFINXZDINX-NEXT: beqz a4, .LBB1_4
; RV32IZFINXZDINX-NEXT: # %bb.3:
; RV32IZFINXZDINX-NEXT: addi a3, a5, -1
; RV32IZFINXZDINX-NEXT: .LBB1_4:
; RV32IZFINXZDINX-NEXT: feq.d a1, s0, s0
; RV32IZFINXZDINX-NEXT: neg a5, a1
; RV32IZFINXZDINX-NEXT: and a1, a5, a3
; RV32IZFINXZDINX-NEXT: neg a2, a2
; RV32IZFINXZDINX-NEXT: and a0, a2, a0
; RV32IZFINXZDINX-NEXT: neg a2, a4
; RV32IZFINXZDINX-NEXT: or a0, a2, a0
; RV32IZFINXZDINX-NEXT: and a0, a5, a0
; RV32IZFINXZDINX-NEXT: and a1, a2, a3
; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
Expand Down Expand Up @@ -347,30 +346,29 @@ define i64 @test_ceil_si64(double %x) nounwind {
; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI5_0)
; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI5_0+4)(a2)
; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI5_0)(a2)
; RV32IZFINXZDINX-NEXT: fle.d a2, a2, s0
; RV32IZFINXZDINX-NEXT: lui a4, %hi(.LCPI5_1)
; RV32IZFINXZDINX-NEXT: lw a5, %lo(.LCPI5_1+4)(a4)
; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI5_1)(a4)
; RV32IZFINXZDINX-NEXT: fle.d a6, a2, s0
; RV32IZFINXZDINX-NEXT: neg a2, a6
; RV32IZFINXZDINX-NEXT: and a0, a2, a0
; RV32IZFINXZDINX-NEXT: flt.d a4, a4, s0
; RV32IZFINXZDINX-NEXT: neg a2, a4
; RV32IZFINXZDINX-NEXT: or a0, a2, a0
; RV32IZFINXZDINX-NEXT: feq.d a2, s0, s0
; RV32IZFINXZDINX-NEXT: neg a2, a2
; RV32IZFINXZDINX-NEXT: lui a5, 524288
; RV32IZFINXZDINX-NEXT: li a4, 1
; RV32IZFINXZDINX-NEXT: lui a3, 524288
; RV32IZFINXZDINX-NEXT: bne a2, a4, .LBB5_2
; RV32IZFINXZDINX-NEXT: beqz a6, .LBB5_2
; RV32IZFINXZDINX-NEXT: # %bb.1:
; RV32IZFINXZDINX-NEXT: mv a3, a1
; RV32IZFINXZDINX-NEXT: .LBB5_2:
; RV32IZFINXZDINX-NEXT: lui a1, %hi(.LCPI5_1)
; RV32IZFINXZDINX-NEXT: lw a6, %lo(.LCPI5_1)(a1)
; RV32IZFINXZDINX-NEXT: lw a7, %lo(.LCPI5_1+4)(a1)
; RV32IZFINXZDINX-NEXT: flt.d a4, a6, s0
; RV32IZFINXZDINX-NEXT: and a0, a2, a0
; RV32IZFINXZDINX-NEXT: beqz a4, .LBB5_4
; RV32IZFINXZDINX-NEXT: # %bb.3:
; RV32IZFINXZDINX-NEXT: addi a3, a5, -1
; RV32IZFINXZDINX-NEXT: .LBB5_4:
; RV32IZFINXZDINX-NEXT: feq.d a1, s0, s0
; RV32IZFINXZDINX-NEXT: neg a5, a1
; RV32IZFINXZDINX-NEXT: and a1, a5, a3
; RV32IZFINXZDINX-NEXT: neg a2, a2
; RV32IZFINXZDINX-NEXT: and a0, a2, a0
; RV32IZFINXZDINX-NEXT: neg a2, a4
; RV32IZFINXZDINX-NEXT: or a0, a2, a0
; RV32IZFINXZDINX-NEXT: and a0, a5, a0
; RV32IZFINXZDINX-NEXT: and a1, a2, a3
; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
Expand Down Expand Up @@ -592,30 +590,29 @@ define i64 @test_trunc_si64(double %x) nounwind {
; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI9_0)
; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI9_0+4)(a2)
; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI9_0)(a2)
; RV32IZFINXZDINX-NEXT: fle.d a2, a2, s0
; RV32IZFINXZDINX-NEXT: lui a4, %hi(.LCPI9_1)
; RV32IZFINXZDINX-NEXT: lw a5, %lo(.LCPI9_1+4)(a4)
; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI9_1)(a4)
; RV32IZFINXZDINX-NEXT: fle.d a6, a2, s0
; RV32IZFINXZDINX-NEXT: neg a2, a6
; RV32IZFINXZDINX-NEXT: and a0, a2, a0
; RV32IZFINXZDINX-NEXT: flt.d a4, a4, s0
; RV32IZFINXZDINX-NEXT: neg a2, a4
; RV32IZFINXZDINX-NEXT: or a0, a2, a0
; RV32IZFINXZDINX-NEXT: feq.d a2, s0, s0
; RV32IZFINXZDINX-NEXT: neg a2, a2
; RV32IZFINXZDINX-NEXT: lui a5, 524288
; RV32IZFINXZDINX-NEXT: li a4, 1
; RV32IZFINXZDINX-NEXT: lui a3, 524288
; RV32IZFINXZDINX-NEXT: bne a2, a4, .LBB9_2
; RV32IZFINXZDINX-NEXT: beqz a6, .LBB9_2
; RV32IZFINXZDINX-NEXT: # %bb.1:
; RV32IZFINXZDINX-NEXT: mv a3, a1
; RV32IZFINXZDINX-NEXT: .LBB9_2:
; RV32IZFINXZDINX-NEXT: lui a1, %hi(.LCPI9_1)
; RV32IZFINXZDINX-NEXT: lw a6, %lo(.LCPI9_1)(a1)
; RV32IZFINXZDINX-NEXT: lw a7, %lo(.LCPI9_1+4)(a1)
; RV32IZFINXZDINX-NEXT: flt.d a4, a6, s0
; RV32IZFINXZDINX-NEXT: and a0, a2, a0
; RV32IZFINXZDINX-NEXT: beqz a4, .LBB9_4
; RV32IZFINXZDINX-NEXT: # %bb.3:
; RV32IZFINXZDINX-NEXT: addi a3, a5, -1
; RV32IZFINXZDINX-NEXT: .LBB9_4:
; RV32IZFINXZDINX-NEXT: feq.d a1, s0, s0
; RV32IZFINXZDINX-NEXT: neg a5, a1
; RV32IZFINXZDINX-NEXT: and a1, a5, a3
; RV32IZFINXZDINX-NEXT: neg a2, a2
; RV32IZFINXZDINX-NEXT: and a0, a2, a0
; RV32IZFINXZDINX-NEXT: neg a2, a4
; RV32IZFINXZDINX-NEXT: or a0, a2, a0
; RV32IZFINXZDINX-NEXT: and a0, a5, a0
; RV32IZFINXZDINX-NEXT: and a1, a2, a3
; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
Expand Down Expand Up @@ -837,30 +834,29 @@ define i64 @test_round_si64(double %x) nounwind {
; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI13_0)
; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI13_0+4)(a2)
; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI13_0)(a2)
; RV32IZFINXZDINX-NEXT: fle.d a2, a2, s0
; RV32IZFINXZDINX-NEXT: lui a4, %hi(.LCPI13_1)
; RV32IZFINXZDINX-NEXT: lw a5, %lo(.LCPI13_1+4)(a4)
; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI13_1)(a4)
; RV32IZFINXZDINX-NEXT: fle.d a6, a2, s0
; RV32IZFINXZDINX-NEXT: neg a2, a6
; RV32IZFINXZDINX-NEXT: and a0, a2, a0
; RV32IZFINXZDINX-NEXT: flt.d a4, a4, s0
; RV32IZFINXZDINX-NEXT: neg a2, a4
; RV32IZFINXZDINX-NEXT: or a0, a2, a0
; RV32IZFINXZDINX-NEXT: feq.d a2, s0, s0
; RV32IZFINXZDINX-NEXT: neg a2, a2
; RV32IZFINXZDINX-NEXT: lui a5, 524288
; RV32IZFINXZDINX-NEXT: li a4, 1
; RV32IZFINXZDINX-NEXT: lui a3, 524288
; RV32IZFINXZDINX-NEXT: bne a2, a4, .LBB13_2
; RV32IZFINXZDINX-NEXT: beqz a6, .LBB13_2
; RV32IZFINXZDINX-NEXT: # %bb.1:
; RV32IZFINXZDINX-NEXT: mv a3, a1
; RV32IZFINXZDINX-NEXT: .LBB13_2:
; RV32IZFINXZDINX-NEXT: lui a1, %hi(.LCPI13_1)
; RV32IZFINXZDINX-NEXT: lw a6, %lo(.LCPI13_1)(a1)
; RV32IZFINXZDINX-NEXT: lw a7, %lo(.LCPI13_1+4)(a1)
; RV32IZFINXZDINX-NEXT: flt.d a4, a6, s0
; RV32IZFINXZDINX-NEXT: and a0, a2, a0
; RV32IZFINXZDINX-NEXT: beqz a4, .LBB13_4
; RV32IZFINXZDINX-NEXT: # %bb.3:
; RV32IZFINXZDINX-NEXT: addi a3, a5, -1
; RV32IZFINXZDINX-NEXT: .LBB13_4:
; RV32IZFINXZDINX-NEXT: feq.d a1, s0, s0
; RV32IZFINXZDINX-NEXT: neg a5, a1
; RV32IZFINXZDINX-NEXT: and a1, a5, a3
; RV32IZFINXZDINX-NEXT: neg a2, a2
; RV32IZFINXZDINX-NEXT: and a0, a2, a0
; RV32IZFINXZDINX-NEXT: neg a2, a4
; RV32IZFINXZDINX-NEXT: or a0, a2, a0
; RV32IZFINXZDINX-NEXT: and a0, a5, a0
; RV32IZFINXZDINX-NEXT: and a1, a2, a3
; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
Expand Down Expand Up @@ -1082,30 +1078,29 @@ define i64 @test_roundeven_si64(double %x) nounwind {
; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI17_0)
; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI17_0+4)(a2)
; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI17_0)(a2)
; RV32IZFINXZDINX-NEXT: fle.d a2, a2, s0
; RV32IZFINXZDINX-NEXT: lui a4, %hi(.LCPI17_1)
; RV32IZFINXZDINX-NEXT: lw a5, %lo(.LCPI17_1+4)(a4)
; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI17_1)(a4)
; RV32IZFINXZDINX-NEXT: fle.d a6, a2, s0
; RV32IZFINXZDINX-NEXT: neg a2, a6
; RV32IZFINXZDINX-NEXT: and a0, a2, a0
; RV32IZFINXZDINX-NEXT: flt.d a4, a4, s0
; RV32IZFINXZDINX-NEXT: neg a2, a4
; RV32IZFINXZDINX-NEXT: or a0, a2, a0
; RV32IZFINXZDINX-NEXT: feq.d a2, s0, s0
; RV32IZFINXZDINX-NEXT: neg a2, a2
; RV32IZFINXZDINX-NEXT: lui a5, 524288
; RV32IZFINXZDINX-NEXT: li a4, 1
; RV32IZFINXZDINX-NEXT: lui a3, 524288
; RV32IZFINXZDINX-NEXT: bne a2, a4, .LBB17_2
; RV32IZFINXZDINX-NEXT: beqz a6, .LBB17_2
; RV32IZFINXZDINX-NEXT: # %bb.1:
; RV32IZFINXZDINX-NEXT: mv a3, a1
; RV32IZFINXZDINX-NEXT: .LBB17_2:
; RV32IZFINXZDINX-NEXT: lui a1, %hi(.LCPI17_1)
; RV32IZFINXZDINX-NEXT: lw a6, %lo(.LCPI17_1)(a1)
; RV32IZFINXZDINX-NEXT: lw a7, %lo(.LCPI17_1+4)(a1)
; RV32IZFINXZDINX-NEXT: flt.d a4, a6, s0
; RV32IZFINXZDINX-NEXT: and a0, a2, a0
; RV32IZFINXZDINX-NEXT: beqz a4, .LBB17_4
; RV32IZFINXZDINX-NEXT: # %bb.3:
; RV32IZFINXZDINX-NEXT: addi a3, a5, -1
; RV32IZFINXZDINX-NEXT: .LBB17_4:
; RV32IZFINXZDINX-NEXT: feq.d a1, s0, s0
; RV32IZFINXZDINX-NEXT: neg a5, a1
; RV32IZFINXZDINX-NEXT: and a1, a5, a3
; RV32IZFINXZDINX-NEXT: neg a2, a2
; RV32IZFINXZDINX-NEXT: and a0, a2, a0
; RV32IZFINXZDINX-NEXT: neg a2, a4
; RV32IZFINXZDINX-NEXT: or a0, a2, a0
; RV32IZFINXZDINX-NEXT: and a0, a5, a0
; RV32IZFINXZDINX-NEXT: and a1, a2, a3
; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
Expand Down Expand Up @@ -1327,30 +1322,29 @@ define i64 @test_rint_si64(double %x) nounwind {
; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI21_0)
; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI21_0+4)(a2)
; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI21_0)(a2)
; RV32IZFINXZDINX-NEXT: fle.d a2, a2, s0
; RV32IZFINXZDINX-NEXT: lui a4, %hi(.LCPI21_1)
; RV32IZFINXZDINX-NEXT: lw a5, %lo(.LCPI21_1+4)(a4)
; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI21_1)(a4)
; RV32IZFINXZDINX-NEXT: fle.d a6, a2, s0
; RV32IZFINXZDINX-NEXT: neg a2, a6
; RV32IZFINXZDINX-NEXT: and a0, a2, a0
; RV32IZFINXZDINX-NEXT: flt.d a4, a4, s0
; RV32IZFINXZDINX-NEXT: neg a2, a4
; RV32IZFINXZDINX-NEXT: or a0, a2, a0
; RV32IZFINXZDINX-NEXT: feq.d a2, s0, s0
; RV32IZFINXZDINX-NEXT: neg a2, a2
; RV32IZFINXZDINX-NEXT: lui a5, 524288
; RV32IZFINXZDINX-NEXT: li a4, 1
; RV32IZFINXZDINX-NEXT: lui a3, 524288
; RV32IZFINXZDINX-NEXT: bne a2, a4, .LBB21_2
; RV32IZFINXZDINX-NEXT: beqz a6, .LBB21_2
; RV32IZFINXZDINX-NEXT: # %bb.1:
; RV32IZFINXZDINX-NEXT: mv a3, a1
; RV32IZFINXZDINX-NEXT: .LBB21_2:
; RV32IZFINXZDINX-NEXT: lui a1, %hi(.LCPI21_1)
; RV32IZFINXZDINX-NEXT: lw a6, %lo(.LCPI21_1)(a1)
; RV32IZFINXZDINX-NEXT: lw a7, %lo(.LCPI21_1+4)(a1)
; RV32IZFINXZDINX-NEXT: flt.d a4, a6, s0
; RV32IZFINXZDINX-NEXT: and a0, a2, a0
; RV32IZFINXZDINX-NEXT: beqz a4, .LBB21_4
; RV32IZFINXZDINX-NEXT: # %bb.3:
; RV32IZFINXZDINX-NEXT: addi a3, a5, -1
; RV32IZFINXZDINX-NEXT: .LBB21_4:
; RV32IZFINXZDINX-NEXT: feq.d a1, s0, s0
; RV32IZFINXZDINX-NEXT: neg a5, a1
; RV32IZFINXZDINX-NEXT: and a1, a5, a3
; RV32IZFINXZDINX-NEXT: neg a2, a2
; RV32IZFINXZDINX-NEXT: and a0, a2, a0
; RV32IZFINXZDINX-NEXT: neg a2, a4
; RV32IZFINXZDINX-NEXT: or a0, a2, a0
; RV32IZFINXZDINX-NEXT: and a0, a5, a0
; RV32IZFINXZDINX-NEXT: and a1, a2, a3
; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
Expand Down
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