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Reapply "[AArch64][NFC] Switch to LiveRegUnits (#87313)" #96840

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Reapply "[AArch64][NFC] Switch to LiveRegUnits (#87313)" #96840

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32 changes: 16 additions & 16 deletions llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -197,6 +197,7 @@
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/CodeGen/LivePhysRegs.h"
#include "llvm/CodeGen/LiveRegUnits.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
Expand Down Expand Up @@ -1007,7 +1008,7 @@ void AArch64FrameLowering::emitZeroCallUsedRegs(BitVector RegsToZero,
}
}

static void getLiveRegsForEntryMBB(LivePhysRegs &LiveRegs,
static void getLiveRegsForEntryMBB(LiveRegUnits &LiveRegs,
const MachineBasicBlock &MBB) {
const MachineFunction *MF = MBB.getParent();
LiveRegs.addLiveIns(MBB);
Expand Down Expand Up @@ -1040,16 +1041,18 @@ static Register findScratchNonCalleeSaveRegister(MachineBasicBlock *MBB) {

const AArch64Subtarget &Subtarget = MF->getSubtarget<AArch64Subtarget>();
const AArch64RegisterInfo &TRI = *Subtarget.getRegisterInfo();
LivePhysRegs LiveRegs(TRI);
LiveRegUnits LiveRegs(TRI);
getLiveRegsForEntryMBB(LiveRegs, *MBB);

// Prefer X9 since it was historically used for the prologue scratch reg.
const MachineRegisterInfo &MRI = MF->getRegInfo();
if (LiveRegs.available(MRI, AArch64::X9))
if (LiveRegs.available(AArch64::X9))
return AArch64::X9;

for (unsigned Reg : AArch64::GPR64RegClass) {
if (LiveRegs.available(MRI, Reg))
BitVector Allocatable =
TRI.getAllocatableSet(*MF, TRI.getRegClass(AArch64::GPR64RegClassID));

for (unsigned Reg : Allocatable.set_bits()) {
if (LiveRegs.available(Reg))
return Reg;
}
return AArch64::NoRegister;
Expand All @@ -1065,14 +1068,11 @@ bool AArch64FrameLowering::canUseAsPrologue(
const AArch64FunctionInfo *AFI = MF->getInfo<AArch64FunctionInfo>();

if (AFI->hasSwiftAsyncContext()) {
const AArch64RegisterInfo &TRI = *Subtarget.getRegisterInfo();
const MachineRegisterInfo &MRI = MF->getRegInfo();
LivePhysRegs LiveRegs(TRI);
LiveRegUnits LiveRegs(*RegInfo);
getLiveRegsForEntryMBB(LiveRegs, MBB);
// The StoreSwiftAsyncContext clobbers X16 and X17. Make sure they are
// available.
if (!LiveRegs.available(MRI, AArch64::X16) ||
!LiveRegs.available(MRI, AArch64::X17))
if (!LiveRegs.available(AArch64::X16) || !LiveRegs.available(AArch64::X17))
return false;
}

Expand Down Expand Up @@ -1664,7 +1664,7 @@ static void emitDefineCFAWithFP(MachineFunction &MF, MachineBasicBlock &MBB,
/// Collect live registers from the end of \p MI's parent up to (including) \p
/// MI in \p LiveRegs.
static void getLivePhysRegsUpTo(MachineInstr &MI, const TargetRegisterInfo &TRI,
LivePhysRegs &LiveRegs) {
LiveRegUnits &LiveRegs) {

MachineBasicBlock &MBB = *MI.getParent();
LiveRegs.addLiveOuts(MBB);
Expand Down Expand Up @@ -1702,7 +1702,7 @@ void AArch64FrameLowering::emitPrologue(MachineFunction &MF,
NonFrameStart->getFlag(MachineInstr::FrameSetup))
++NonFrameStart;

LivePhysRegs LiveRegs(*TRI);
LiveRegUnits LiveRegs(*TRI);
if (NonFrameStart != MBB.end()) {
getLivePhysRegsUpTo(*NonFrameStart, *TRI, LiveRegs);
// Ignore registers used for stack management for now.
Expand All @@ -1726,7 +1726,7 @@ void AArch64FrameLowering::emitPrologue(MachineFunction &MF,
make_range(MBB.instr_begin(), NonFrameStart->getIterator())) {
for (auto &Op : MI.operands())
if (Op.isReg() && Op.isDef())
assert(!LiveRegs.contains(Op.getReg()) &&
assert(LiveRegs.available(Op.getReg()) &&
"live register clobbered by inserted prologue instructions");
}
});
Expand Down Expand Up @@ -4333,7 +4333,7 @@ MachineBasicBlock::iterator tryMergeAdjacentSTG(MachineBasicBlock::iterator II,
// FIXME : This approach of bailing out from merge is conservative in
// some ways like even if stg loops are not present after merge the
// insert list, this liveness check is done (which is not needed).
LivePhysRegs LiveRegs(*(MBB->getParent()->getSubtarget().getRegisterInfo()));
LiveRegUnits LiveRegs(*(MBB->getParent()->getSubtarget().getRegisterInfo()));
LiveRegs.addLiveOuts(*MBB);
for (auto I = MBB->rbegin();; ++I) {
MachineInstr &MI = *I;
Expand All @@ -4342,7 +4342,7 @@ MachineBasicBlock::iterator tryMergeAdjacentSTG(MachineBasicBlock::iterator II,
LiveRegs.stepBackward(*I);
}
InsertI++;
if (LiveRegs.contains(AArch64::NZCV))
if (!LiveRegs.available(AArch64::NZCV))
return InsertI;

llvm::stable_sort(Instrs,
Expand Down
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