Skip to content

[RISCV] Don't expand zero stride vp.strided.load if SEW>XLEN #98924

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 1 commit into from
Jul 16, 2024
Merged

[RISCV] Don't expand zero stride vp.strided.load if SEW>XLEN #98924

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
5 changes: 5 additions & 0 deletions llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -174,6 +174,11 @@ bool RISCVCodeGenPrepare::expandVPStrideLoad(IntrinsicInst &II) {
m_Value(BasePtr), m_Zero(), m_AllOnes(), m_Value(VL))))
return false;

// If SEW>XLEN then a splat will get lowered as a zero strided load anyway, so
// avoid expanding here.
if (II.getType()->getScalarSizeInBits() > ST->getXLen())
return false;

if (!isKnownNonZero(VL, {*DL, DT, nullptr, &II}))
return false;

Expand Down
8 changes: 0 additions & 8 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpload.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -674,17 +674,9 @@ define <4 x half> @zero_strided_unmasked_vpload_4f16(ptr %ptr) {
define <4 x i64> @zero_strided_vadd.vx(<4 x i64> %v, ptr %ptr) {
; CHECK-RV32-LABEL: zero_strided_vadd.vx:
; CHECK-RV32: # %bb.0:
; CHECK-RV32-NEXT: addi sp, sp, -16
; CHECK-RV32-NEXT: .cfi_def_cfa_offset 16
; CHECK-RV32-NEXT: lw a1, 4(a0)
; CHECK-RV32-NEXT: lw a0, 0(a0)
; CHECK-RV32-NEXT: sw a1, 12(sp)
; CHECK-RV32-NEXT: sw a0, 8(sp)
; CHECK-RV32-NEXT: addi a0, sp, 8
; CHECK-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-RV32-NEXT: vlse64.v v10, (a0), zero
; CHECK-RV32-NEXT: vadd.vv v8, v8, v10
; CHECK-RV32-NEXT: addi sp, sp, 16
; CHECK-RV32-NEXT: ret
;
; CHECK-RV64-LABEL: zero_strided_vadd.vx:
Expand Down
8 changes: 0 additions & 8 deletions llvm/test/CodeGen/RISCV/rvv/strided-vpload.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -826,17 +826,9 @@ define <vscale x 1 x half> @zero_strided_unmasked_vpload_nxv1f16(ptr %ptr) {
define <vscale x 1 x i64> @zero_strided_vadd.vx(<vscale x 1 x i64> %v, ptr %ptr) {
; CHECK-RV32-LABEL: zero_strided_vadd.vx:
; CHECK-RV32: # %bb.0:
; CHECK-RV32-NEXT: addi sp, sp, -16
; CHECK-RV32-NEXT: .cfi_def_cfa_offset 16
; CHECK-RV32-NEXT: lw a1, 4(a0)
; CHECK-RV32-NEXT: lw a0, 0(a0)
; CHECK-RV32-NEXT: sw a1, 12(sp)
; CHECK-RV32-NEXT: sw a0, 8(sp)
; CHECK-RV32-NEXT: addi a0, sp, 8
; CHECK-RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; CHECK-RV32-NEXT: vlse64.v v9, (a0), zero
; CHECK-RV32-NEXT: vadd.vv v8, v8, v9
; CHECK-RV32-NEXT: addi sp, sp, 16
; CHECK-RV32-NEXT: ret
;
; CHECK-RV64-LABEL: zero_strided_vadd.vx:
Expand Down