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[NVPTX] Support fence instruction #99649

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Merged
merged 3 commits into from
Jul 24, 2024
Merged

[NVPTX] Support fence instruction #99649

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08cd286
[NVPTX] Support fence instruction
gonzalobg Jul 15, 2024
ee55b37
Fixup: use INT_MEMBAR_SYS instead of redefining the membar.sys opcode
gonzalobg Jul 16, 2024
4985c56
[NVPTX] Add comment to clarify pre sm70 behavior
gonzalobg Jul 19, 2024
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28 changes: 28 additions & 0 deletions llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
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Original file line number Diff line number Diff line change
Expand Up @@ -3908,3 +3908,31 @@ def : Pat <
(V2I32toI64
(INT_NVVM_PRMT (I64toI32H Int64Regs:$a), (i32 0), (i32 0x0123)),
(INT_NVVM_PRMT (I64toI32L Int64Regs:$a), (i32 0), (i32 0x0123)))>;


////////////////////////////////////////////////////////////////////////////////
// PTX Fence instructions
////////////////////////////////////////////////////////////////////////////////

def atomic_thread_fence_seq_cst_sys :
NVPTXInst<(outs), (ins), "fence.sc.sys;", []>,
Requires<[hasPTX<60>, hasSM<70>]>;
def atomic_thread_fence_acq_rel_sys :
NVPTXInst<(outs), (ins), "fence.acq_rel.sys;", []>,
Requires<[hasPTX<60>, hasSM<70>]>;

def : Pat<(atomic_fence (i64 4), (i64 1)), (atomic_thread_fence_acq_rel_sys)>, // acquire(4) sys(1)
Requires<[hasPTX<60>, hasSM<70>]>;
def : Pat<(atomic_fence (i64 5), (i64 1)), (atomic_thread_fence_acq_rel_sys)>, // release(5) sys(1)
Requires<[hasPTX<60>, hasSM<70>]>;
def : Pat<(atomic_fence (i64 6), (i64 1)), (atomic_thread_fence_acq_rel_sys)>, // acq_rel(6) sys(1)
Requires<[hasPTX<60>, hasSM<70>]>;
def : Pat<(atomic_fence (i64 7), (i64 1)), (atomic_thread_fence_seq_cst_sys)>, // seq_cst(7) sys(1)
Requires<[hasPTX<60>, hasSM<70>]>;


// If PTX<60 or SM<70, we fall back to MEMBAR:
def : Pat<(atomic_fence (i64 4), (i64 1)), (INT_MEMBAR_SYS)>; // acquire(4) sys(1)
def : Pat<(atomic_fence (i64 5), (i64 1)), (INT_MEMBAR_SYS)>; // release(5) sys(1)
def : Pat<(atomic_fence (i64 6), (i64 1)), (INT_MEMBAR_SYS)>; // acq_rel(6) sys(1)
def : Pat<(atomic_fence (i64 7), (i64 1)), (INT_MEMBAR_SYS)>; // seq_cst(7) sys(1)
36 changes: 36 additions & 0 deletions llvm/test/CodeGen/NVPTX/fence.ll
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@@ -0,0 +1,36 @@
; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s --check-prefix=SM60
; RUN: %if ptxas %{ llc < %s -march=nvptx64 -mcpu=sm_20 | %ptxas-verify %}
; RUN: llc < %s -march=nvptx64 -mcpu=sm_70 -mattr=+ptx60 | FileCheck %s --check-prefix=SM70
; RUN: %if ptxas-12.2 %{ llc < %s -march=nvptx64 -mcpu=sm_70 -mattr=+ptx60 | %ptxas-verify -arch=sm_70 %}

; CHECK-LABEL: fence_sc_sys
define void @fence_sc_sys() local_unnamed_addr {
; SM60: membar.sys
; SM70: fence.sc.sys
fence seq_cst
ret void
}

; CHECK-LABEL: fence_acq_rel_sys
define void @fence_acq_rel_sys() local_unnamed_addr {
; SM60: membar.sys
; SM70: fence.acq_rel.sys
fence acq_rel
ret void
}

; CHECK-LABEL: fence_release_sys
define void @fence_release_sys() local_unnamed_addr {
; SM60: membar.sys
; SM70: fence.acq_rel.sys
fence release
ret void
}

; CHECK-LABEL: fence_acquire_sys
define void @fence_acquire_sys() local_unnamed_addr {
; SM60: membar.sys
; SM70: fence.acq_rel.sys
fence acquire
ret void
}