Fix incorrect privilege mode detection causing failed dret riscv-dv tests #2301
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| wait (dut_vif.dut_cb.ctrl_fsm_cs == FLUSH); | ||
| clk_vif.wait_clks(2); | ||
| check_priv_mode(PRIV_LVL_M); | ||
| check_priv_mode(init_operating_mode); |
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When you get an illegal instruction it must trap in M-mode regardless of what the initial operating mode is.
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Well, I think the time of checking was on trap exit. If the design here was to test the mode on trap entry, we'll probably have to discuss how to rewrite this module. The wait on line 1126 here can not capture the flush signal on trap entry. In this specific testcase(riscv_dret_test), the previous functions before the wait line have a handshake mechanism and blocks the wait line until handshake finished, so the first flush on trap entry signal will not be captured in this case. That's probably why I think this checking is wrong.
| virtual task check_stimulus(); | ||
| forever begin | ||
| wait (dut_vif.dut_cb.dret === 1'b1); | ||
| @(negedge dut_vif.dut_cb.dret); |
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I think you're changing what this test does now. This test sees whether there is a DRET instruction and makes sure it is detected as illegal. Have you configured your Ibex to support DRET?
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Yes I have the dret enabled, and it is only a legal instruction in debug mode.
I don't think I am changing the test here. Somehow, the wait line failed to capture here sometime, only negedge can correctly triggers all the time.
The testbench of the riscv-dv flow failed to compare the privilege mode of the DUT correctly and failing the riscv_dret_test. The testbench assumes the DUT will always be in machine mode while different random seeds can generate a testcase that would bring the DUT into either user mode or machine mode at the point of comparison.
Some seeds of the riscv_dret_test that leads to failure:
VCS: 1574
XLM: 28930
This commit fixed the comparison and make riscv_dret_test of the riscv-dv pass under either circumstances.
