GitHub - luk3Sky/Building-A-Processor---Project: Design of a simulated 8-bit single-cycle processor using Verilog HDL, which includes an ALU, a register file and other control logic

luk3Sky / Building-A-Processor---Project Public

Design of a simulated 8-bit single-cycle processor using Verilog HDL, which includes an ALU, a register file and other control logic

Notifications

Name		Name	Last commit message	Last commit date
Latest commit History 27 Commits
ALU		ALU
REGISTER FILE		REGISTER FILE
CO224 - Lab 5 - Building a Simple Processor.pdf		CO224 - Lab 5 - Building a Simple Processor.pdf
CO224Assembler.c		CO224Assembler.c
CPU.v		CPU.v
Icarus_Verilog_GTKWave_guide.pdf		Icarus_Verilog_GTKWave_guide.pdf
Lab 5 skeleton code.pdf		Lab 5 skeleton code.pdf
Lab06_G30.v		Lab06_G30.v
Lab06_Group09.v		Lab06_Group09.v
Lab06_Group30.zip		Lab06_Group30.zip
Processor.v		Processor.v
R.vcd		R.vcd
alu.v		alu.v
alu.vvp		alu.vvp
aluBehavioralLevel.v		aluBehavioralLevel.v
cpu.vvp		cpu.vvp
data_mem.v		data_mem.v
memory.v		memory.v
new.v		new.v
new.vvp		new.vvp
processor.vvp		processor.vvp
processor1.v		processor1.v
project.v		project.v
regfile.v		regfile.v
registerFile.v		registerFile.v
test.txt		test.txt
testbench.vcd		testbench.vcd
tt.v		tt.v
tt.vvp		tt.vvp