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CPUInterrupts, setting up registers, etc: interactions between the OS and the CPUInterrupts, setting up registers, etc: interactions between the OS and the CPUfeatureNew featuresNew features
Description
Currently, interrupts are not handled at all by the kernel, which sometimes results in freezes or crashes during testing. Uncaught exceptions result in fatal triple faults, and implementing support for x86-64 interrupts using the Interrupt Descriptor Table
(IDT
) and custom interrupt routines should avoid this behaviour.
It should also allow for a better logging/understanding of these exceptions.
Requirements:
- Set up the required types and infrastructure for interacting with the
IDT
. - Implement
Interrupt Service Routines
(ISR
) for all 21 interrupts, at least with some sort of logging, if not handling, of the associated error.
Useful resources
- osdev wiki articles about the
IDT
,IST
s and how to set them up: Interrupt Descriptor Table, Interrupt Service Routines - AMD's official x86-64 programmer documentation: Vol 1-5.
- Articles from phil-opp's rust osdev blog: CPU exceptions ; Double-faults and setting up custom hardware interrupts in Hardware Interrupts
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CPUInterrupts, setting up registers, etc: interactions between the OS and the CPUInterrupts, setting up registers, etc: interactions between the OS and the CPUfeatureNew featuresNew features