Add Cortex-R support

boot/zephyr/Kconfig

@@ -340,7 +340,7 @@ config BOOT_SIGNATURE_KEY_FILE
 
 config MCUBOOT_CLEANUP_ARM_CORE
 	bool "Perform core cleanup before chain-load the application"
-	depends on CPU_CORTEX_M
+	depends on CPU_CORTEX_M || CPU_CORTEX_R5
 	default y
 	help
 	  This option instructs MCUboot to perform a clean-up of a set of

boot/zephyr/arm_cleanup.c

@@ -1,21 +1,38 @@
 /*
  * Copyright (c) 2020 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Siemens Mobility GmbH
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include <stdint.h>
+#include <zephyr/irq.h>
+#include "zephyr/sys/util_macro.h"
 #include <zephyr/toolchain.h>
 
+#ifdef CONFIG_CPU_CORTEX_M
 #include <cmsis_core.h>
+#endif
 #if CONFIG_CPU_HAS_NXP_MPU
 #include <fsl_sysmpu.h>
 #endif
 
-void cleanup_arm_nvic(void) {
+#ifndef CONFIG_CPU_CORTEX_M
+
+#ifdef CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER
+extern void z_soc_irq_eoi(unsigned int irq);
+#else
+#include <zephyr/drivers/interrupt_controller/gic.h>
+#endif
+
+#endif /* CONFIG_CPU_CORTEX_M */
+
+void cleanup_arm_interrupts(void) {
 	/* Allow any pending interrupts to be recognized */
 	__ISB();
 	__disable_irq();
 
+#ifdef CONFIG_CPU_CORTEX_M
 	/* Disable NVIC interrupts */
 	for (uint8_t i = 0; i < ARRAY_SIZE(NVIC->ICER); i++) {
 		NVIC->ICER[i] = 0xFFFFFFFF;
@@ -24,11 +41,27 @@ void cleanup_arm_nvic(void) {
 	for (uint8_t i = 0; i < ARRAY_SIZE(NVIC->ICPR); i++) {
 		NVIC->ICPR[i] = 0xFFFFFFFF;
 	}
+#else
+
+	for (unsigned int i = 0; i < CONFIG_NUM_IRQS; ++i) {
+		irq_disable(i);
+	}
+
+	for (unsigned int i = 0; i < CONFIG_NUM_IRQS; ++i) {
+#ifdef CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER
+		z_soc_irq_eoi(i);
+#else
+		arm_gic_eoi(i);
+#endif /* CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER */
+	}
+
+#endif /* CONFIG_CPU_CORTEX_M */
 }
 
 #if CONFIG_CPU_HAS_ARM_MPU
 __weak void z_arm_clear_arm_mpu_config(void)
 {
+#ifdef CONFIG_CPU_CORTEX_M
 	int i;
 
 	int num_regions =
@@ -37,6 +70,32 @@ __weak void z_arm_clear_arm_mpu_config(void)
 	for (i = 0; i < num_regions; i++) {
 		ARM_MPU_ClrRegion(i);
 	}
+#else
+	uint8_t i;
+	uint8_t num_regions;
+	uint32_t mpu_type_register;
+
+	// disable MPU
+	__asm__(
+		"	mrc p15, 0, r0, c1, c0, 0\n"
+		"	bic r0, #1\n"
+		"	mcr p15, 0, r0, c1, c0, 0\n"
+		"	isb\n"
+		::: "r0");
+
+	// the number of MPU regions is stored in bits 15:8 of the MPU type register
+	__asm__ volatile("mrc p15, 0, %0, c0, c0, 4\n" : "=r" (mpu_type_register) ::);
+	num_regions = (uint8_t) ((mpu_type_register >> 8) & BIT_MASK(8));
+
+	for (i = 0; i < num_regions; ++i) {
+		// select region in the MPU and clear the region size field
+		__asm__ volatile(
+			"	mov r0, #0\n"
+			"	mcr p15, 0, %0, c6, c2, 0\n"
+			"	mcr p15, 0, r0, c6, c1, 2\n"
+			:: "r" (i) : "r0");
+	}
+#endif /* CONFIG_CPU_CORTEX_M */
 }
 #elif CONFIG_CPU_HAS_NXP_MPU
 __weak void z_arm_clear_arm_mpu_config(void)

boot/zephyr/include/arm_cleanup.h

@@ -11,7 +11,7 @@
 /**
  * Cleanup interrupt priority and interupt enable registers.
  */
-void cleanup_arm_nvic(void);
+void cleanup_arm_interrupts(void);
 
 #if defined(CONFIG_CPU_HAS_ARM_MPU) || defined(CONFIG_CPU_HAS_NXP_MPU)
 /**

boot/zephyr/main.c

@@ -2,6 +2,7 @@
  * Copyright (c) 2012-2014 Wind River Systems, Inc.
  * Copyright (c) 2020 Arm Limited
  * Copyright (c) 2021-2023 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Siemens Mobility GmbH
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
@@ -31,7 +32,7 @@
 #include <zephyr/cache.h>
 #endif
 
-#if defined(CONFIG_ARM)
+#if defined(CONFIG_CPU_CORTEX_M)
 #include <cmsis_core.h>
 #endif
 
@@ -141,8 +142,19 @@ extern void *_vector_table_pointer;
 #endif
 
 struct arm_vector_table {
+#ifdef CONFIG_CPU_CORTEX_M
     uint32_t msp;
     uint32_t reset;
+#else
+    uint32_t reset;
+    uint32_t undef_instruction;
+    uint32_t svc;
+    uint32_t abort_prefetch;
+    uint32_t abort_data;
+    uint32_t reserved;
+    uint32_t irq;
+    uint32_t fiq;
+#endif
 };
 
 static void do_boot(struct boot_rsp *rsp)
@@ -189,7 +201,7 @@ static void do_boot(struct boot_rsp *rsp)
     usb_disable();
 #endif
 #if CONFIG_MCUBOOT_CLEANUP_ARM_CORE
-    cleanup_arm_nvic(); /* cleanup NVIC registers */
+    cleanup_arm_interrupts(); /* disable and acknowledge all interrupts */
 
 #if defined(CONFIG_BOOT_DISABLE_CACHES)
     /* Flush and disable instruction/data caches before chain-loading the application */
@@ -232,10 +244,31 @@ static void do_boot(struct boot_rsp *rsp)
 #endif
 #endif /* CONFIG_BOOT_INTR_VEC_RELOC */
 
+#ifdef CONFIG_CPU_CORTEX_M
     __set_MSP(vt->msp);
+#endif
+
 #if CONFIG_MCUBOOT_CLEANUP_ARM_CORE
+#ifdef CONFIG_CPU_CORTEX_M
     __set_CONTROL(0x00); /* application will configures core on its own */
     __ISB();
+#else
+    /* Set mode to supervisor and A, I and F bit as described in the
+     * Cortex R5 TRM */
+    __asm__ volatile(
+        "   mrs r0, CPSR\n"
+        /* change mode bits to supervisor */
+        "   bic r0, #0x1f\n"
+        "   orr r0, #0x13\n"
+        /* set the A, I and F bit */
+        "   mov r1, #0b111\n"
+        "   lsl r1, #0x6\n"
+        "   orr r0, r1\n"
+
+        "   msr CPSR, r0\n"
+        ::: "r0", "r1");
+#endif /* CONFIG_CPU_CORTEX_M */
+
 #endif
 #if CONFIG_MCUBOOT_CLEANUP_RAM
     __asm__ volatile (
@@ -263,7 +296,17 @@ static void do_boot(struct boot_rsp *rsp)
         : "r0", "r1", "r2", "r3", "memory"
     );
 #else
+
+#ifdef CONFIG_CPU_CORTEX_M
     ((void (*)(void))vt->reset)();
+#else
+    /* Some architectures like the Cortex-R run in thumb mode but reset into ARM
+     * mode. To do the switch into ARM mode an explicit branch with exchange
+     * instruction set is needed
+     */
+    __asm__("bx %0\n" : : "r" (&vt->reset));
+#endif
+
 #endif
 }
 

docs/release-notes.d/add-cortex-r-support-00-basic.md

@@ -0,0 +1 @@
+- Added support for booting Cortex-R5 images

docs/release-notes.d/add-cortex-r-support-01-cleanup-core.md

@@ -0,0 +1 @@
+- Add support for cleaning up the Cortex-R core before final jumping