Lift to Vitis HLS 2020.2 and PYNQ 2.7

.clang-format

@@ -0,0 +1,5 @@
+---
+Language: Cpp
+BasedOnStyle: WebKit
+...
+

.gitignore

@@ -0,0 +1,3 @@
+**/accel
+**/vitis_hls.log
+zynq/build

zynq/Makefile

@@ -3,7 +3,7 @@ BUILD_DIR = build
 SCRIPT_DIR = tcl
 
 # Executables
-VIVADO_HLS = vivado_hls
+VIVADO_HLS = vitis_hls
 VIVADO = vivado
 
 .PHONY: all setup ip bit clean

zynq/hls/mmult_fixed/hls.tcl

@@ -2,12 +2,16 @@
 set src_dir "."
 open_project accel
 set_top mmult_hw
-add_files $src_dir/mmult_fixed.cpp
+add_files $src_dir/mmult_float.cpp
 add_files -tb $src_dir/mmult_test.cpp
-open_solution "solution0"
+
+open_solution "solution0" -flow_target vivado
 set_part {xc7z020clg484-1}
 create_clock -period 10 -name default
+set_clock_uncertainty 12.5%
+
+config_compile -pipeline_loops 0
 csim_design -clean
 csynth_design
 close_project
-exit
+exit

zynq/hls/mmult_fixed/mmult.h

@@ -1,6 +1,7 @@
 
-#include <assert.h>
 #include <ap_axi_sdata.h>
+#include <assert.h>
+#include <hls_stream.h>
 
 // Type definition of matrix elements
 typedef ap_int<8> w_T;
@@ -15,14 +16,14 @@ typedef unsigned out_bit_T;
 typedef unsigned long long axi_T;
 
 // Datatype widths in bits
-#define W_WIDTH (sizeof(w_T)*8)
-#define IN_WIDTH (sizeof(in_T)*8)
-#define OUT_WIDTH (sizeof(out_T)*8)
+#define W_WIDTH (sizeof(w_T) * 8)
+#define IN_WIDTH (sizeof(in_T) * 8)
+#define OUT_WIDTH (sizeof(out_T) * 8)
 
 // Data type ratio between data type and axi width
-#define W_WIDTH_RATIO (8*sizeof(axi_T)/W_WIDTH)
-#define IN_WIDTH_RATIO (8*sizeof(axi_T)/IN_WIDTH)
-#define OUT_WIDTH_RATIO (8*sizeof(axi_T)/OUT_WIDTH)
+#define W_WIDTH_RATIO (8 * sizeof(axi_T) / W_WIDTH)
+#define IN_WIDTH_RATIO (8 * sizeof(axi_T) / IN_WIDTH)
+#define OUT_WIDTH_RATIO (8 * sizeof(axi_T) / OUT_WIDTH)
 
 // Matrix dimensions specifications
 #define BATCH 8192
@@ -34,21 +35,21 @@ typedef unsigned long long axi_T;
 // #define TILING
 
 // Input/Output Stream Size
-#define IS_SIZE ((CLASSES+OUT_WIDTH_RATIO-1)/OUT_WIDTH_RATIO+CLASSES*FEAT/W_WIDTH_RATIO+BATCH*FEAT/IN_WIDTH_RATIO)
-#define OS_SIZE (BATCH*((CLASSES+OUT_WIDTH_RATIO-1)/OUT_WIDTH_RATIO))
+#define IS_SIZE ((CLASSES + OUT_WIDTH_RATIO - 1) / OUT_WIDTH_RATIO + CLASSES * FEAT / W_WIDTH_RATIO + BATCH * FEAT / IN_WIDTH_RATIO)
+#define OS_SIZE (BATCH * ((CLASSES + OUT_WIDTH_RATIO - 1) / OUT_WIDTH_RATIO))
 
 // AXI settings (leave it fixed)
-#define AXI_DATA (sizeof(axi_T)*8)
+#define AXI_DATA (sizeof(axi_T) * 8)
 #define AXI_U 4
 #define AXI_TI 5
 #define AXI_TD 5
 
 // AXI interface
-typedef ap_axiu<AXI_DATA,AXI_U,AXI_TI,AXI_TD> AXI_VAL;
+typedef ap_axiu<AXI_DATA, AXI_U, AXI_TI, AXI_TD> AXI_VAL;
 
 // Matrix Multiply prototype
-void mmult_hw (AXI_VAL in_stream[IS_SIZE],AXI_VAL out_stream[OS_SIZE]);
+void mmult_hw(hls::stream<AXI_VAL>& in_stream, hls::stream<AXI_VAL>& out_stream);
 
 // AXI stream push and pop
-axi_T pop_stream(AXI_VAL const &e);
-AXI_VAL push_stream(axi_T const &v, bool last);
+axi_T pop_stream(hls::stream<AXI_VAL>& in_stream);
+AXI_VAL push_stream(axi_T const& v, bool last);

zynq/hls/mmult_fixed/mmult_fixed.cpp

@@ -5,92 +5,101 @@
 
 // --------------------------------------------------------------------
 // function to be accelerated in HW wrapped with AXI4-Stream interface
-void mmult_hw (AXI_VAL in_stream[IS_SIZE], AXI_VAL out_stream[OS_SIZE])
+void mmult_hw(hls::stream<AXI_VAL>& in_stream, hls::stream<AXI_VAL>& out_stream)
 {
 #pragma HLS INTERFACE s_axilite port=return     bundle=CONTROL_BUS
 #pragma HLS INTERFACE axis      port=in_stream
 #pragma HLS INTERFACE axis      port=out_stream
 
-	// Assertions (to avoid out of array bound writes)
-	assert(BATCH%TILING==0);
-	assert(FEAT%W_WIDTH_RATIO==0);
-	assert(FEAT%IN_WIDTH_RATIO==0);
-	assert((BATCH*CLASSES)%OUT_WIDTH_RATIO==0);
-
-	// Hardware memory buffers
-	out_T offset_buf[CLASSES];
-	w_T weight_buf[CLASSES][FEAT];
-	in_T in_buf[TILING][FEAT];
-	out_T out_buf[TILING][CLASSES];
-
-	// Input and output AXI stream indices
-	int is_idx = 0;
-	int os_idx = 0;
-
-	// Stream in offset vector
-	// CSE548 TODO
-
-	// Stream in weight matrix
-	// CSE548 TODO
-
-	// Iterate over tiles
-	LT: for (int t = 0; t < BATCH; t+=TILING) {
-
-		// Stream in input tile
-		// CSE548 TODO
-
-		// Perform matrix multiplication
-		L1: for (int i = 0; i < TILING; i++) {
-			// Iterate over output classes
-			L2: for (int j = 0; j < CLASSES; j++) {
-				// Perform the dot product
-				out_T tmp = offset_buf[j];
-				L3: for(int k = 0; k < FEAT; k++) {
-					out_T mult = in_buf[i][k] * weight_buf[j][k];
-					tmp += mult;
-				}
-				out_buf[i][j] = tmp;
-			}
-		}
-
-		// Stream out output matrix
-		// CSE548 TODO
-	}
+    // Assertions (to avoid out of array bound writes)
+    assert(BATCH % TILING == 0);
+    assert(FEAT % W_WIDTH_RATIO == 0);
+    assert(FEAT % IN_WIDTH_RATIO == 0);
+    assert((BATCH * CLASSES) % OUT_WIDTH_RATIO == 0);
+
+    // Hardware memory buffers
+    out_T offset_buf[CLASSES];
+    w_T weight_buf[CLASSES][FEAT];
+    in_T in_buf[TILING][FEAT];
+    out_T out_buf[TILING][CLASSES];
+
+#pragma HLS BIND_STORAGE    variable=offset_buf type=RAM_T2P
+#pragma HLS BIND_STORAGE    variable=weight_buf type=RAM_T2P
+#pragma HLS BIND_STORAGE    variable=in_buf     type=RAM_T2P
+#pragma HLS BIND_STORAGE    variable=out_buf    type=RAM_T2P
+
+    // Input and output AXI stream indices
+    int is_idx = 0;
+    int os_idx = 0;
+
+// Stream in offset vector
+// CSE548 TODO
+
+// Stream in weight matrix
+// CSE548 TODO
+
+// Iterate over tiles
+LT:
+    for (int t = 0; t < BATCH; t += TILING) {
+
+    // Stream in input tile
+    // CSE548 TODO
+
+    // Perform matrix multiplication
+    L1:
+        for (int i = 0; i < TILING; i++) {
+        // Iterate over output classes
+        L2:
+            for (int j = 0; j < CLASSES; j++) {
+                // Perform the dot product
+                out_T tmp = offset_buf[j];
+            L3:
+                for (int k = 0; k < FEAT; k++) {
+                    out_T mult = in_buf[i][k] * weight_buf[j][k];
+                    tmp += mult;
+                }
+                out_buf[i][j] = tmp;
+            }
+        }
+
+        // Stream out output matrix
+        // CSE548 TODO
+    }
 }
 
-
 // --------------------------------------------------------
 // functions to insert and extract elements from an axi stream
 // includes conversion to correct data type
-axi_T pop_stream(AXI_VAL const &e)
+axi_T pop_stream(hls::stream<AXI_VAL>& in_stream)
 {
 #pragma HLS INLINE
+    AXI_VAL e;
+    in_stream.read(e);
 
-	axi_T ret = e.data;
+    axi_T ret = e.data;
 
-	volatile ap_uint<sizeof(axi_T)> strb = e.strb;
-	volatile ap_uint<sizeof(axi_T)> keep = e.keep;
-	volatile ap_uint<AXI_U> user = e.user;
-	volatile ap_uint<1> last = e.last;
-	volatile ap_uint<AXI_TI> id = e.id;
-	volatile ap_uint<AXI_TD> dest = e.dest;
+    volatile ap_uint<sizeof(axi_T)> strb = e.strb;
+    volatile ap_uint<sizeof(axi_T)> keep = e.keep;
+    volatile ap_uint<AXI_U> user = e.user;
+    volatile ap_uint<1> last = e.last;
+    volatile ap_uint<AXI_TI> id = e.id;
+    volatile ap_uint<AXI_TD> dest = e.dest;
 
-	return ret;
+    return ret;
 }
 
-AXI_VAL push_stream(axi_T const &v, bool last = false)
+AXI_VAL push_stream(axi_T const& v, bool last = false)
 {
 #pragma HLS INLINE
 
-	AXI_VAL e;
+    AXI_VAL e;
 
-	e.data = v;
-	e.strb = (1<<sizeof(axi_T))-1;
-	e.keep = (1<<sizeof(axi_T))-1;
-	e.user = 0;
-	e.last = last ? 1 : 0;
-	e.id = 0;
-	e.dest = 0;
-	return e;
+    e.data = v;
+    e.strb = (1 << sizeof(axi_T)) - 1;
+    e.keep = (1 << sizeof(axi_T)) - 1;
+    e.user = 0;
+    e.last = last ? 1 : 0;
+    e.id = 0;
+    e.dest = 0;
+    return e;
 }
-