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opal/timer: add code to check if rtdtsc is core invariant #2596

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Merged
merged 1 commit into from
Dec 17, 2016

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hjelmn
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@hjelmn hjelmn commented Dec 16, 2016

Newer x86 processors have a core invariant tsc. On these systems it is
safe to use the rtdtsc instruction as a monotonic timer. This commit
adds a new function to the opal timer code to check if the timer
backend is monotonic. On x86 it checks the appropriate bit and on
other architectures it parrots back the OPAL_TIMER_MONOTONIC value.

Signed-off-by: Nathan Hjelm [email protected]

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hjelmn commented Dec 16, 2016

This is a enhancement that helps #2591 and #2592 when running on newer Intel processors where the tsc is core invariant. We still will need to find something for older Intel processors.

Newer x86 processors have a core invariant tsc. On these systems it is
safe to use the rtdtsc instruction as a monotonic timer. This commit
adds a new function to the opal timer code to check if the timer
backend is monotonic. On x86 it checks the appropriate bit and on
other architectures it parrots back the OPAL_TIMER_MONOTONIC value.

Signed-off-by: Nathan Hjelm <[email protected]>
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@hjelmn have you tested this on KNL?

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bot:lanl:retest

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hjelmn commented Dec 17, 2016

@hppritcha Haven't tested this on KNL yet. Being a newer processor I would hope the invariant tsc is available.

BTW, I now I have reports back from 3 code teams. They all report getting the same or better performance as 1.6.5 on TLCC2 systems when using the tsc timer. CTS-1 systems show a similar speedup.

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4 participants